40% or 66 % higher capacitance "equal to 130nm "and little supple voltage scaling !
Thus Power can not be lower based on physics Power being proportional to C and V*V . I am loosing all respect for TSMC and GF marketing.
Rick or anyone else any comment?
Valid concerns with the increased capacitance, however that only points out a potential increase in dynamic power. Recently, leakage power has been of major concern in Deep Submicron Planar technologies. This power is consumed while the gates are not switching and historically have contributed much of the power. Perhaps finfets offer the benefit of reduced leakage power.....
I guess I should add intel BS marketing as well.
Paul O. CEO has been talking about a finfet and winning mobile for past 3 years. yet intel still not shipping mobile atoms using finfet. In fact Paul will be pushed out of intel before a singe cell phone or table chip ship with finfet ships.
I hear uncompetitive 22nm finfet atoms too high power and shipping slipping to 2014 . I think Rick you found the problem. Capacitance is too high and finfets increase not lower power .
Anil Jain said “ FinFETs bring a 66 percent increase in gate capacitance per micron compared to today’s-28nm process, back up to the level of the 130-nm planar node”. I disagree. At the device level the transistor drive current is improved by high gate capacitance resulted from higher permittivity of the high-k dielectric. However, performance at high operating clock frequency can be negatively impacted by the increased gate capacitance. To minimize this penalty Intel uses the unique HK/MG (high K such as HfO2)/Metal electrode that give intrinsically superior electrostatic control or short channel effect and reduced stand-by power reducing gate current. Therefore, Intel’s HK/MG will provide high performance through higher gate capacitance and concurrently scale down the gate length of the transistor. That is why Intel’s 22nm FinFETs are in high volume manufacturing over a year, and the 14nm FinFETs will be manufactured in 2014. Recently, major foundries, TSMC, Samsung, and others announced to adopt FinFET technology at 14nm and manufacture in 2014, skipping the 22nm to catch up with Intel. However, the successful implementation of FinFET technology will be much easier at the 22nm than at the 14nm node because of the lack of process and manufacturing learning at the 22nm node, resulting in further behind Intel.
The "gate capacitance" is no longer just the inversion gate capacitance. In fact, inversion gate capacitance is just a small portion of the total transistor capacitance. FinFET has significantly higher parasitic capacitance than planar devices, and that's just one of the few reasons even Intel FinFET did not the 50% reduction of active power that was originally claimed.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.