A spokesperson for TSMC has told me that they won't be putting out any SEM cross-sections of the 16FF process until ICs made using the process have been sold.
Once that happens third parties can buy some chips, take a saw to a chip and take their own microphotographs. So TSMC may leave it up to those third parties or release some of their own.
"New ARM Architectures for Servers: 64 bit, Virtualization, and Energy Efficiency".
I want to see cross sections.
I want to know Fin height variations within a die and across the wafer.
I don't need some marketing BS
On April 9, ARM talk on "New ARM Architectures for Servers: 64 bit, Virtualization, and Energy Efficiency". Attend event in San Jose or on-line: http://sites.ieee.org/scv-cs/ by IEEE Computer Society Santa Clara Valley
"The test chip was implemented using a commercially available tool chain and design services provided by companies associated with ARM and TSMC."
Did TSMC provide by any chance SEM cross sections?
I am curious about fin height variations for example
what's the shape look like?
Do they look similar to Intel
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...