I like the approach to saving power and thus extending battery life. Given the CVFsq nature of power would it make for a more efficient GPU if it was made more parallel and ran at a much slower clock frequency? Given the frequency is squared in the power calculation I would expect significant power savings through increasing the silicon used to provide the graphics processing. Just a thought (has this been done already?).
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.