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resistion
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re: Intel previews server and Thunderbolt chips
resistion   4/13/2013 3:23:14 PM
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The lowest TDP Sandy bridge and corresponding performance is about same as lowest TDP of haswell and its corresponding performance. It can be found in published data that the 22 nm finfet transition took more of a performance hit in order to reduce power.

jaybus0
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re: Intel previews server and Thunderbolt chips
jaybus0   4/13/2013 2:49:33 PM
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The current one is 17W. The new one is down to 13W. More interesting will be the E5 10 core chips at 70W. It will be possible to get 4 of these in a 1U chassis. That's 40 2.5+ GHz cores, 80 hyper-threads, with at least Ivy Bridge performance levels, and at least half a TB of DRAM in a 1U. It is interesting. It is not clear to me that the ARM and Atom server chips will win here. Better performance per Watt is important, but only as long as it can maintain the same or better performance per volume unit. If a 2U space of ARM or Atom chips is needed to run as many VMs as a 1U of E5s, then which really costs less?

TarraTarra!
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re: Intel previews server and Thunderbolt chips
TarraTarra!   4/13/2013 5:16:24 AM
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It is interesting that the new E3 power ranges from 17W, 45W to 87W. They must be really hand-picking the 17W parts because the true power seems to be in the 60W range. Wonder how much yield they can get for the low power part.

kjdsfkjdshfkdshfvc
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re: Intel previews server and Thunderbolt chips
kjdsfkjdshfkdshfvc   4/12/2013 3:38:48 PM
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Cool stuff. http://bit.ly/IC4m9t



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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