The lowest TDP Sandy bridge and corresponding performance is about same as lowest TDP of haswell and its corresponding performance. It can be found in published data that the 22 nm finfet transition took more of a performance hit in order to reduce power.
The current one is 17W. The new one is down to 13W. More interesting will be the E5 10 core chips at 70W. It will be possible to get 4 of these in a 1U chassis. That's 40 2.5+ GHz cores, 80 hyper-threads, with at least Ivy Bridge performance levels, and at least half a TB of DRAM in a 1U. It is interesting. It is not clear to me that the ARM and Atom server chips will win here. Better performance per Watt is important, but only as long as it can maintain the same or better performance per volume unit. If a 2U space of ARM or Atom chips is needed to run as many VMs as a 1U of E5s, then which really costs less?
It is interesting that the new E3 power ranges from 17W, 45W to 87W. They must be really hand-picking the 17W parts because the true power seems to be in the 60W range. Wonder how much yield they can get for the low power part.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.