"Even if EUV hits its targets, the 10nm node also requires use of self-aligning techniques with immersion lithography to minimize the need for EUV to just some critical layers. TSMC also is developing a so-called G-rule that automates the tricky process of handling color conflicts in double patterning."
It would be implied that no EUV layers would be best otherwise why all the trouble with the double patterning.
God also gave electrons mean free paths, so I doubt EUV or E-beam are the intended windows for lithography.
Burn Lin should have retired as the Holy Father of Immersion, basically saving an industry which made another obviously foolish bet on X-ray lithography (oh, sorry: EUV lithography) and while saving us from a 157nm black hole. The trouble with such success is it can breed hubris. Lin's E-beam direct write has had a similar history to X-ray. The end of optical seems around the corner, billions are spent on alternatives, all fail; now, the end of optical seems even closer, so the failures are renamed (EUV and maskless), more resources are wasted, but Mother Nature doesn't pay attention to marketing-created name-changes. Refocusing from X-ray to EBDW means instead of the overwhelming challenges of source, resist, and mask/blank, we have the overwhelming challenges of source, resist, throughput, and data path.
Who does direct write?
ASML bought SVG and ASML killed it.
Direct write goes back to Eaton?
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved electron beam lithography method for creating an exposure pattern having unprecedented resolution in an electron sensitive surface.
This is accomplished in accordance with this invention by patternwise treating an electron sensitive surface to a high resolution pattern of low-energy electrons rather than high-energy electrons.
When the separation between the pointed electrode and the surface being treated is less than about 1 nm, the electron clouds of the atoms at the apex of the pointed electrode and at the surface opposite the apex touch, and a tunnel current path is established between the apex of the pointed electrode and the surface. When the separation is more than about 3 nm, electrons must leave the pointed source via field emission. When the separation is between about 1 and 3 nm, both current effects are experienced. In any case, the area of the surface receiving the electrons has a diameter roughly equal to the distance between the point source of the electrons and the target surface.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.