bunch of hyping -
some very recent quotes from ASML (UBS Technology conference)
"we are starting this later this year"
"This is really essential in terms, because if you have this machine on its own, it does overlay accuracy 5-nanometers to 6-nanometers. 5-nanometers to 6-nanometers is not good enough for double-patterning, you need to have something closer to 2-nanometers to have a double-patterning accuracy that allows yields to be acceptable and yields are related to prices wafer prices et cetera, et cetera.
So in fact, this is the key, having this is the key to be able to do 20-nanometer processing in production at acceptable cost and we have one major customer who is engaging in this and we are starting this later this year. This was immersion, but immersion, water immersion and double-patterning immersion going to be with us for a long time, you could almost say forever....
The more you start to look into the details where an eagle is it looks like when you go to a 14-nanometer logic design, which they will call 10 or 11 or 9 in terms of nomenclature they also call 20-nanometer 16 and 14 and it’s one big mess in terms of how do you call it. But if you look at it in terms of lithography point of view, 14-nanometer lines which is the next generation. It comes after 20 is awfully, awfully difficult in double-patterning left below multiple-patterning and if at all you are able to do it, you are imposing yourself a lot of design restrictions, limitations and also at significant higher cost.
This kind of explains TSMC's recent push. What I don't understand in all this is the 4 years they project for 450 immersion. Why will it take so long if there are customers that want to start running 450 wafers in 2015?
RobDinsmore, what customers want to start running and what may be technical/economically feasible are not always in line.
I liked their 2017 wafer start projection "if we keep growing". Moore's law may apply to chip features, but I don't think it applies to companies ... though continuous unsupported growth has often been in business models... till they fail.
TSMC goal/objective for 2013 is to increase 28nm HKMG / 28 SiON to more than 50% ,
NVDA is delayed because they can't get 28nm HKMG wafers!!!
TSMC FinFet = 20 nm design rules = muted die shrink
this is the real world
my manager just came back from a visit with all the foundries. His report called all the post 20nm work (finfet, EUV, 450mm ) as "power point". EUV being the best examples. .....still fundamental physic uncertainty but TSMC, GF have it on roadmap for 2015 production.
most of our future designs will be targeted to the last moore's law node "28nn"
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.