Having spent many years in ASIC support for customers doing high speed digital design I can say for sure that there was and needs to be a tight coupling between the design team and the layout group. All too often, the design team (working in Verilog/VHDL) was too disconnected from the physical ramifications of what they were coding that it took some "high energy" meetings between the designers and layout groups to work on finding a solution. Often times there were many trade offs being made live over the layout/placement with the needed visual feedback, I can't imagine having an optimal solution with a large physical/cultural/language separation.
Indeed. Many of us working on the front end side of IC design never liked the idea of "throw it over the wall" to the backend team, even in the days when that was more feasible. Too much loss of communication and feedback between the two teams usually leads to a suboptimal result.
Even the author's own observations -- the need for expertise in signal integrity, high-speed I/O integration, DFT, package design, etc on the backend team makes the argument even more powerful that it is not a good idea to just throw the database over the wall to the backend team, cross your fingers and hope for the best.
Nothing beats co-location, and that can only be accomplished with an in-house backend team.
I wonder how many of those out-house layout teams are out there. With foundries clampping on information (design rules, models, etc.), what would be a viable path for such companies to survive? The only way seems to be for foundries to take over design.
Automated analog layout has always lagged digital layout until now. This task can be completed in a manner of minutes versus weeks due to an optimization process incorporated into a software by Analog Rails. Comment as you wish on this being a commercial or look at the solution that will considerably shorten design times.
I too disagree with this article. In my 16 years of experience, the continual increase in process and EDA tool complexity (see cadence 5.1 to 6.1 transition) has made the need for a local layout team even more important.
Moronda is dead on, another sales pitch from Jack Harding about eSilicon, we gave these guys a tried. They don't have many of the capabilities that they claimed, and not that good at what they do have. This guy is a baffoon, and there a lot better design services company out there.
I'm sorry but this is obviously a total sales pitch from esilicon. Here's how I read this story. Layout is really tough and we here at esilicon know what we are doing. So quit doing layout at your company, fire all your layout engineers, and farm it out to us. Come spend millions of dollars at esilicon. Then, we will also up sell you on the rest of our services like IP and manufacturing.
I think outsourcing can be a big pain in the butt. There is nothing that says it can't go bad too. What if I get your worst layout team on my project? I don't want to be on the phone with a bunch of people that barely speak english.
Harding, what have you done at esilicon? Why are you still private? Why haven't you gone public or been acquired? You've been around for years and years. What's going on there? If I was lead investor in esilicon, I would fire you for not closing on a successful exit.
I think these board of directors are just clueless sometimes. Crosspoint, Crescendo, Fremont, Investor Growth, don't you want a return on your investment? Why is this guy still in charge? Hold someone accountable for not executing to an acquisition or IPO.
My guess is that nobody cares about acquiring a design services company. There is huge competition in that space.
But say for high speed circuits, RF or analog designs, it is quite necessary for the layout and circuit guys sit close to each other. Our circuit team benefitted in terms of turn around time because the layout engineer was sitting in a neighbouring cubicle. I somehow feel that the quality will suffer if the layout moves out of the team.
I think you are right for fabless companies. For the major semiconductor companies that develop their own processes, they need to build their own standard cell libraries. This is a very powerful tool for competitiveness. I have seen similar chips from two companies with big differences in size due to the basic cell even though the process was similar. I don't see IDMs moving away from internal layout.
Statistically speaking, I think you may be correct. But, there is a lot to be said to having a "tight" coupling between architecture and layout. Having done back end stuff for 25+ years I can't tell you how many times the architects thought they had Carte Blanche over what they could do and include on the die. It was only after many very energetic face to face "dungeon" like sessions where we met a happy middle ground.
When the backend is isolated like this, I'm sure assembling a bunch of hard IP around some on chip interconnect/fabric at frequencies/power/area that may not be pushing the envelope the 1st pass is fine. But other then that, you're going to really benefit by having that close communication between architecture/logic/layout/circuits.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.