The story with Intel is they will do their own thing, and can stay independent of HMC. Check out the latest word out on Haswell's L4 cache - it's actually DRAM made by Intel itself (on its 22 nm trigate process).
I don't think HMC benefits or benefits from NV since larger latency and less frequent access may be expected. But if there is a new type of memory that is very much like DRAM working memory (maybe STT?) perhaps it could be considered as well.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.