The story with Intel is they will do their own thing, and can stay independent of HMC. Check out the latest word out on Haswell's L4 cache - it's actually DRAM made by Intel itself (on its 22 nm trigate process).
I don't think HMC benefits or benefits from NV since larger latency and less frequent access may be expected. But if there is a new type of memory that is very much like DRAM working memory (maybe STT?) perhaps it could be considered as well.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.