There are so many definitions for efficiency, so cannot comment on your number of 70%
In any case, there is a strong possibility that the next 1X generation will be conventional floating gate with wrap around IPD and only after that 3D NAND will come.
It's a game of chicken among the four manufacturers. Who will go quadruple patterning with floating gate, and who will go 3D with charge-trapping. TLC is just to delay this fairly terrifying choice. It's a good topic for a betting pool.
“MLC to TLC is not doubling…”
What matters for the storage is Mbit/ unit area.
One method is to use Triple-Level- Cell and the other is to shrink the memory cell and have larger memory density. If error correction and stability can be guaranteed than TLC is a viable option for increasing the density. Of course the endurance is another topic.
Memory products have low margin of profit so using EUV is not the first option. In the future, NAND memory will go vertical and have 3D structures. 3D structures will have a relaxed pitch and the vertical integration will help increase the memory density.
It is an amazing achievement by itself when you look at the SEM picture of a 64 bits wordline and triple level per cell. I think we have a tendency to overlook and take for granted this kind of technology marvel.
Next step will be 3D with charge trapping cell where the channel is made out of poly. That will give a huge boost to the NAND density with a relaxed design rules
The processing of 8 or more cycles of device layers cannot be considered the same cost as a single cycle. There is multiplied material consumption as well as processing time. So this 3D cost-effectiveness thinking is self-deceit.
This point hits home when, in the SADP flow, the "spacer dep", "spacer etch" and "mandrel etch" were tagged as separate cost items in the cost stacks. If we applied this to 3D NAND specific process, we would have cost stacks 16 or 32 x higher!