Resistion: Even if you create a PCM structure where the active material is in the form of an annulus, at sub-20nm dimensions I think the device will still have to rely on thermal cross coupling within the device structure to keep the reset current density at a level that will avoid the consequences of element separation and electro-migration. This will also mean that in a close packed matrix of those devices the device- to-device separation will be approximately the same as the the thermal coupling distant and you will suffer the consequences of thermal cross talk.
In one of my earlier PCM papers in EETimes I looked briefly at a structure similar to the one you are suggesting. I characterized it as a Wrap Around Link (WAL)PCM structure and attempted to relate its likely performance to that of flat link PCM structures. If I remember it was described in a Numonyx patent. I am not aware that anybody is working on constructing memory matrix using that structure. I suppose it is just possible that it could form part of the IBM-SKH program.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.