TSMC is right in finally accepting that there is a long way to go in terms of design methodology yield improvement etc. before they can hope to use 3D die stacking for jelly - bean like Smart Phones. Since they seem to be putting a lot of their competitive eggs ( vis a vis Intel ? ) into the basket of stacking dissimilar dice by 3D, wish the EE Times reporter had quizzed them on specifics and not let them get away with "motherhood" type statements.
Oh well !
Few topic come to mind if there is a follow up to this article with TSMC:
-what is TSMC's plan to bring the costs down in 3D IC integration?
-why isn't TSMC actively promoting / nurturing ecosystem partners that can perhaps develop cost-effective technologies (such as interposers, cooling technologies, etc) than organic efforts?
-is there a product vision / road map for heterogeneous integration?
Chipmonk - you posted this back in November and you were right on the money.
3D is too costly for low priced SoCs
"Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU."
Sure 10nm can be done with ebeam....but at what cost is the right question.
Not cost effective for mainstream SOC. moores law roadmap is becomming clearer. 28nm is lowest cost per transistor and where bulk of cost sensitive SOC made
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists from incubators join Peter Clarke in debate.