The reason SOI is looking more attractive is the lack of value for Taiwan Semi 16. From 20 to 16 die size does not shrink (even slightly bigger for many blocks) I just don't see who is going to pay more for a wafer if die size does not shrink. By definition...there is no Moore's Law from 20 to 16.
I don't get Taiwan semi's road map anymore
IBM invented PDSOI, FDSOI, ET(extremely thin) SOI technologies. The PDSOI was very successful, but FDSOI including UTBB and ETSOI are not in manufacturing at any technology node today. This is because one of the critical issues with FDSOI is its scalerability. For the 28nm FDSOI a very thin SOI thickness or transistor channel thickness of 7nm is required to suppress its transistor leakage current, while for the 28nm planer bulk the transistor channel thickness is controlled by a combination of halo and retrograded implants, providing a fully depleted and significantly deeper than 7nm. That is why the planer bulk 28nm has been in high volume manufacturing by Intel, and major foundries for over two years. ST claimed last year that its 28nm FDSOI was ready for manufacturing, but is not yet. ST's 28nm FDSOI seems to be too late to inter the 28nm node market unless its 28nm FDSOI is superier to the planer bulk 28nm. Intel's 22nm FinFETs are in high Volume manufacturing over a year. But Chery dosn't say when ST will manufacture the 22nm FDSOI even though he has claimed on FDSOI having advantage over bulk CMOS or FinFET process. For the 22nm FDSOI the SOI thickness even thinner 4.5nm is required to suppress the transistor leakage current. Comparatively, for the 22nnm FinFET the Fin widh of 22nm that is equivalent to the FDSOI thicknesses of 4.5nm is required. What a big difference! That is why Intel's 22nm FinFETs are in high volume manufacturing over a year, but not 22nm FDSOI, and having difficulties in manufacturing even 28nm FDSOI. Skim
Yes the thin silicon in FDSOI results in very very low transistor current compared to bulk transistors. The ST 28nm FDSOI current is about 50% lower compared to 28HPM.
That is a fundamental issue for circuit blocks
The relatively lower drive current of 28FD has nothing to do with thin Si channel. It's the lack of strain elements that hurts the device. Strain elements are part of 14FD and impressive HW data is already shown (at VLSI and IEDM last year), with AC performance surpassing 22nm FinFET. There is no barrier in adding such elements in a 28nm FDSOI technology, the same way there are 3 versions of 28nm bulk technology.
ST (not TS) seems to be betting the digital part of the house on FDSOI. For BigD, paricularly low power, it may actually work, as long as you don't need exotic analog IP - FDSOI gets kinky with analog.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.