Hardly seems worth the effort. After all, the Si wafer costs about a dime per sq cm. All the cost is in the masking. If it is going to be that complex to go 3D, hardly seems to have an advantage over just tuning the ability to reliably pattern a classic wafer. All the cost goes into the patterning machinery and using it effectively.
Note that the density of the Toshiba chip, 32G cells for 94mm2, implies the cells are about 50 nm x 50 nm, roughly 2.5x the resolution of the lithography.
It turns out that for vertical channel NAND (such as BiCS and TCAT) the total chip cost is an extremely strong function of the taper angle and the vertical gate pitch. If you want to see cost response surfaces for these, check out the study I made at:
This shows that any taper angle more than a few tenths of a degree away from vertical (thus Mr. Esfarjani's "precisely 89.8 degrees" comment) leads to a technology that is uneconomical and that can be undercut by other 3D approaches.
It also shows that lithography is of secondary importance compared to taper angle and vertical gate pitch (thus the "not limited by lithography" comment).
The close-to-90-degree taper angle required for any cost advantage results in challenging etch and fill steps in manufacturing.
It really does look like a classic silicon "conservation of misery" taking shape. Instead of the classic 2D NAND challenges, we see other extremely difficult problems that these manufacturers have to deal with.
It's kind of spurise for me when I saw "high endurance of 10^5 cycles and higher". NAND has been far away from that spec for a few generations, why intel put that back again in the reliability spec of their 3D NAND?
The statement "But a working cell is not enough. You also need high endurance of 10^5 cycles and higher" says a lot! The pBIC technology sounds interesting but until Intel releases die-level reliability test results, all bets are off.