Embedded Systems Conference
Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
Wobbly
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
Wobbly   5/29/2013 3:37:45 PM
NO RATINGS
I think in the NAND market you are getting the first indications of working ReRAM. If vendors are moving to a completely new architecture/technology, how hard are they going to push on the current technology?

resistion
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
resistion   5/29/2013 11:43:47 AM
NO RATINGS
But the cost is additive not reductive with density.

Ron Neale
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
Ron Neale   5/29/2013 9:41:17 AM
NO RATINGS
I think what we might want to call the 1M generation should be added to the list. M for Multi-Chip Package (MCP) where chip stacking, with Through Silicon Vias (TSVs) is used to achieve the required doubling of transistor/memory device density and is likely to play a significant role at about the 19-20nm node. In that way, take your pick for MCP or 3D monolithic, a constant chip footprint (area) will be meet the prediction of Moore's Law independent of the lithographic node.

resistion
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
resistion   5/28/2013 6:19:32 PM
NO RATINGS
I think an even more foreboding implication from Sandisk is that it did NOT pull in 3D NAND, but actually pushed it out two years to 2016.

resistion
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
resistion   5/28/2013 6:17:10 PM
NO RATINGS
Well for NAND, the quadruple patterning to 10 nm would not have been more lithography/masks but certainly more process steps. Hynix did ~15 nm at IEDM two years ago. It would have made more sense to do this for both the 1Y and 1Z nodes, with both 1Y and 1Z closer to 10 nm to offset the potential doubling of costs with quadruple compared to double patterning. Now that 1Y is still 19 nm, it doesn't make much sense. Also possible, too close to 10 nm is too big a risk with S-D tunneling.

any1
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
any1   5/28/2013 5:06:42 PM
NO RATINGS
Peter, I think you have it right. Of course this is all about cost. The profit margins for commodity NAND chips simply are not high enough to justify the costs required to go to a smaller node right now. So the "more than Moore" design optimization was the best/only economical choice. At this point no one is counting on EUV litho coming to the rescue any time soon.

3D Guy
User Rank
Author
re: London Calling: Moore's Law fail at NAND flash node
3D Guy   5/28/2013 3:56:16 PM
NO RATINGS
Maybe SanDisk/Toshiba couldn't get high k working for flash, so they couldn't go to a flat cell and thereby failed to scale down?

<<   <   Page 2 / 2


Radio
NEXT UPCOMING BROADCAST
In conjunction with unveiling of EE Times’ Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. One of Silicon Valley's great contributions to the world has been the demonstration of how the application of entrepreneurship and venture capital to electronics and semiconductor hardware can create wealth with developments in semiconductors, displays, design automation, MEMS and across the breadth of hardware developments. But in recent years concerns have been raised that traditional venture capital has turned its back on hardware-related startups in favor of software and Internet applications and services. Panelists from incubators join Peter Clarke in debate.
Flash Poll
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Special Video Section
Chwan-Jye Foo (C.J Foo), product marketing manager for ...
The LT®3752/LT3752-1 are current mode PWM controllers ...
LED lighting is an important feature in today’s and future ...
Active balancing of series connected battery stacks exists ...
After a four-year absence, Infineon returns to Mobile World ...
A laptop’s 65-watt adapter can be made 6 times smaller and ...
An industry network should have device and data security at ...
The LTC2975 is a four-channel PMBus Power System Manager ...
In this video, a new high speed CMOS output comparator ...
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...
General-purpose DACs have applications in instrumentation, ...
Linear Technology demonstrates its latest measurement ...
10:29
Demos from Maxim Integrated at Electronica 2014 show ...
Bosch CEO Stefan Finkbeiner shows off latest combo and ...
STMicroelectronics demoed this simple gesture control ...
Keysight shows you what signals lurk in real-time at 510MHz ...
TE Connectivity's clear-plastic, full-size model car shows ...
Why culture makes Linear Tech a winner.