I think in the NAND market you are getting the first indications of working ReRAM. If vendors are moving to a completely new architecture/technology, how hard are they going to push on the current technology?
I think what we might want to call the 1M generation should be added to the list. M for Multi-Chip Package (MCP) where chip stacking, with Through Silicon Vias (TSVs) is used to achieve the required doubling of transistor/memory device density and is likely to play a significant role at about the 19-20nm node. In that way, take your pick for MCP or 3D monolithic, a constant chip footprint (area) will be meet the prediction of Moore's Law independent of the lithographic node.
Well for NAND, the quadruple patterning to 10 nm would not have been more lithography/masks but certainly more process steps. Hynix did ~15 nm at IEDM two years ago. It would have made more sense to do this for both the 1Y and 1Z nodes, with both 1Y and 1Z closer to 10 nm to offset the potential doubling of costs with quadruple compared to double patterning. Now that 1Y is still 19 nm, it doesn't make much sense. Also possible, too close to 10 nm is too big a risk with S-D tunneling.
Peter, I think you have it right. Of course this is all about cost. The profit margins for commodity NAND chips simply are not high enough to justify the costs required to go to a smaller node right now. So the "more than Moore" design optimization was the best/only economical choice. At this point no one is counting on EUV litho coming to the rescue any time soon.
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.