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Wobbly
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re: London Calling: Moore's Law fail at NAND flash node
Wobbly   5/29/2013 3:37:45 PM
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I think in the NAND market you are getting the first indications of working ReRAM. If vendors are moving to a completely new architecture/technology, how hard are they going to push on the current technology?

resistion
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re: London Calling: Moore's Law fail at NAND flash node
resistion   5/29/2013 11:43:47 AM
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But the cost is additive not reductive with density.

Ron Neale
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re: London Calling: Moore's Law fail at NAND flash node
Ron Neale   5/29/2013 9:41:17 AM
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I think what we might want to call the 1M generation should be added to the list. M for Multi-Chip Package (MCP) where chip stacking, with Through Silicon Vias (TSVs) is used to achieve the required doubling of transistor/memory device density and is likely to play a significant role at about the 19-20nm node. In that way, take your pick for MCP or 3D monolithic, a constant chip footprint (area) will be meet the prediction of Moore's Law independent of the lithographic node.

resistion
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re: London Calling: Moore's Law fail at NAND flash node
resistion   5/28/2013 6:19:32 PM
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I think an even more foreboding implication from Sandisk is that it did NOT pull in 3D NAND, but actually pushed it out two years to 2016.

resistion
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re: London Calling: Moore's Law fail at NAND flash node
resistion   5/28/2013 6:17:10 PM
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Well for NAND, the quadruple patterning to 10 nm would not have been more lithography/masks but certainly more process steps. Hynix did ~15 nm at IEDM two years ago. It would have made more sense to do this for both the 1Y and 1Z nodes, with both 1Y and 1Z closer to 10 nm to offset the potential doubling of costs with quadruple compared to double patterning. Now that 1Y is still 19 nm, it doesn't make much sense. Also possible, too close to 10 nm is too big a risk with S-D tunneling.

any1
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re: London Calling: Moore's Law fail at NAND flash node
any1   5/28/2013 5:06:42 PM
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Peter, I think you have it right. Of course this is all about cost. The profit margins for commodity NAND chips simply are not high enough to justify the costs required to go to a smaller node right now. So the "more than Moore" design optimization was the best/only economical choice. At this point no one is counting on EUV litho coming to the rescue any time soon.

3D Guy
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re: London Calling: Moore's Law fail at NAND flash node
3D Guy   5/28/2013 3:56:16 PM
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Maybe SanDisk/Toshiba couldn't get high k working for flash, so they couldn't go to a flat cell and thereby failed to scale down?

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