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Max The Magnificent
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re: Xilinx to test FinFET FPGAs in 2013
Max The Magnificent   5/31/2013 8:56:29 PM
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I always liked Jethro Tull's "Thick as a Brick" :-)

Chipguy1
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re: Xilinx to test FinFET FPGAs in 2013
Chipguy1   5/31/2013 3:06:17 PM
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Yes 16 node is really 20 node transistor density (both transistor pitch and metal pitch are same as 20) at higher wafer cost. It makes no sense. Cost per transistor goes up (Moore's law goes backward) Plus if that was not bad enough it is too costly to build and validate design IP for 2 nodes with the same transistor density. This is why Altera, Cisco, Micro Semi and i hear likely another another left for intel. Intel''s 14 nm will have a real 14nm metal system and a real 14nm transistor density

the_floating_ gate
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re: Xilinx to test FinFET FPGAs in 2013
the_floating_ gate   5/31/2013 7:08:57 AM
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How many times does one have to explain to you that 14nm/16nm FinFet applies to 20nm design rules? How does it feel being thick as a brick?

DynamicLogic.US
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re: Xilinx to test FinFET FPGAs in 2013
DynamicLogic.US   5/30/2013 8:05:36 PM
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"16-nm FinFET test chips in 2013 and first products in 2014" More integration than Moore's 18 month cycle. Mobile supercomputer systems on a chip coming...



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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