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Phononscattering
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re: Chipmakers turn to new process for sub-nm DRAM cells
Phononscattering   6/15/2013 10:28:34 PM
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The claims in your patent only mention this stack to be deposited on a semiconductor substrate, not a metal electrode, if I am not mistaken? There is also an important difference: The Material in the ZAZ stack is crystallized. The Al2O3 interlayer is not used to prevent crystallization. There was only a very short time when amorphous HAH or ZAZ stacks were used. Elpida and Micron did this in their 70-100nm products. They switched to crystalline stacks later.

Phononscattering
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re: Chipmakers turn to new process for sub-nm DRAM cells
Phononscattering   6/15/2013 10:05:04 PM
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inventyan: The claims in your patent only mention this stack to be deposited on a semiconductor substrate, not a metal electrode, if I am not mistaken? There is also an important difference: The Material in the ZAZ stack is crystallized. The Al2O3 interlayer is not used to prevent crystallization. There was only a very short time when amorphous HAH or ZAZ stacks were used. Elpida and Micron did this in their 70-100nm products. They switched to crystalline stacks later.

inventyan
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re: Chipmakers turn to new process for sub-nm DRAM cells
inventyan   6/10/2013 3:12:03 PM
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Cann't believe my multilayer (US Patent #6,407,435) is used in actual device now! A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

resistion
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re: Chipmakers turn to new process for sub-nm DRAM cells
resistion   6/9/2013 3:48:58 AM
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Samsung 20 nm DRAM patterning still cost-effective enough, it seems. http://itersnews.com/?p=437

Chipguy1
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re: Chipmakers turn to new process for sub-nm DRAM cells
Chipguy1   6/8/2013 8:16:42 PM
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With micron-elpida merger....world is down to just 3 DRAM players with 75% of the production in Korea. I suspect that might be the endpoint of consolidation and give Samsung an advantage in end devices.

RedSoxRick
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re: Chipmakers turn to new process for sub-nm DRAM cells
RedSoxRick   6/8/2013 3:09:45 PM
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Buried Word Line: This reads like the Patented technology developed by Qimonda

getty
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re: Chipmakers turn to new process for sub-nm DRAM cells
getty   6/8/2013 6:08:10 AM
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Dear Mr. Choe, Please email me. Jiyong Kim(hbt100@naver.com)

resistion
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Manager
re: Chipmakers turn to new process for sub-nm DRAM cells
resistion   6/8/2013 12:00:52 AM
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Hi, last figure cannot be any clearer?

arno_x
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re: Chipmakers turn to new process for sub-nm DRAM cells
arno_x   6/7/2013 10:53:31 PM
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Nice article. Thanks.



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