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betajet
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re: DAC Keynote from James Truchard
betajet   6/19/2013 7:29:51 PM
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Let me ramble a comment here. First, what the spreadsheet did for financial analysis is that it took a format and techniques that had been used for centuries and automated them, so that people could try different inputs and see the results instantly in place of weeks of error-prone calculations. This was a game changer, but not because it involved new ideas -- it just sped up the application of very old ideas. I've been watching CAD/CAE/DA for a long time, and it does a good job of handling details so that you have a good chance at first-pass silicon and PC boards that either work or are at least usable. However, clever design ideas come from clever design engineers who have lots experience and have learned lots of tricks over their careers. I don't see how this is going to be automated any time soon, except in very restricted domains where you don't need to be clever. IMO hardware and software are very different beasts and require very different mind-sets. With hardware, you try to keep things simple and clever so the hardware will be fast and cheap. With software, you have the luxury of cheap complexity, and relatively few opportunities for parallelism that might speed things up. Automatically converting software into fast, parallel hardware sounds attractive, but IMO it's not going to beat a clever designer who really knows the hardware technology to be used. You'll probably end up with bloated FPGAs instead, which should make FPGA vendors happy because those are the chips with big profit margins. At a talk I saw at the recent Design West, one speaker gave an interesting perspective on the VHDL versus Verilog question. He likes people to design FPGAs in VHDL precisely because it doesn't look like software. He finds that Verilog causes people to think FPGAs are like software and come up with poor designs.



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