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Peter Clarke
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re: 28-nm SoC development costs doubled over previous node
Peter Clarke   6/21/2013 9:32:31 AM
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@luting I could not provide a break down of Semico Research's data. They only provide so much information for free. To find out more Semico would like people to buy a 58 page report with 15 tables and 33 graphs. But on a qualitative basis my undertstanding is that the functional and software complexity of leading-edge system chips is increasing. Meanwhile the need to get to market quickly is increasing. The result is that in many geographies equipment makers often rely on the SoC provider to define much of the basic equipment hardware and software functionality while they are working on the plastic casing, the user experience software, the boxing, the documentation, the sales channel distribution and the marketing of the equipment.

luting
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re: 28-nm SoC development costs doubled over previous node
luting   6/20/2013 5:07:34 PM
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Could Author provide break down where those significant increase of silicon and SW comes from?

Peter Clarke
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re: 28-nm SoC development costs doubled over previous node
Peter Clarke   6/20/2013 8:41:23 AM
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We've heard about the software burden on SoC for years -- and about how hard it is for chip companies to get properly paid for the software they provide. Looks like this is really starting to kick in at 28-nm and below. Does the the 9 million unit viability threshold ring true to readers?

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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