The new features of iJTAG 1149.1-2013 enable yield ramp up by using a thing called ECID, Electronic Chip ID, which correlates system test back to the wafer position. They are using this for trackign the die from production to board/system test.
Along with that, I guess, there is a 'free ride' for also preventing counterfeiting through re-marking the part. The part will have a JTAG accessible ECID which tells you what speed grade, temperature grade or pass/fail status of the die. So no longer can one scrunge the trash bins of Intel to find parts which didnt pass and then sell them off as working parts. No longer can you erase the C temperature grade on the top of the chip and mark it as Industrial or AEC or MIL.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.