I like the new approach to advertising. I am wondering if they are using youtube because it is the best vehicle to reach the newer engineers? I would like to have seen some solid details in the adverts: optimized a 10 million gates on a 2Ghz speed system in 10mins(maybe as a sidebar / footnote). For many users the ease of use, the speed of compiles and results matter.
Yes, a clever parody of the Mac vs. PC ads. The RTL optimization pioneered by Oasys does look very interesting, and their claims for runtime and quality of results on large SoCs is quite astonishing.
It seems like all the buzz in EDA these days is about ESL (electronic system level), but here is a company that is taking on the still painful task of optimizing synthesis and timing closure at the chip level for SoCs with tens of millions of gates -- and starting with good old-fashioned RTL.
Their tools are very new, but seem to be generating some buzz of their own. It will be interesting to see how they fare in the very tough EDA business.
Blog Doing Math in FPGAs Tom Burke 0 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...