Samsung actually proposed more options for 3D NAND Flash: TCAT, VSAT and vertical gate. I think they would win any 3D NAND war Toshiba starts.
If such a war can be run, that is. Since the 3D NAND is based on charge trapping in nitride, not floating gate, the nitride charge trapping reliability issues come to fore. The move to charge trapping has not yet preceded the move to 3D-NAND. This technology is still a high-risk technology that has not yet been qualified. Since it cannot prevent charge spreading like floating gate, there is a fundamental issue there.
If Toshiba doesn't buid more NAND capacity then they will loose market share to someone else who will - probably Samsung. It's a high stakes business and you have to be able to pull the trigger when you think the timing is right.
>> With so much die stacking being used in mobiles, it seems inevitable that at some point, it will be easier to "push a process node" by stacking rather than shrinking.
If you look carefully in these die stacking systems, we are not getting the best performance because the software we hope to mine their efficiencies are still sub-optimal. The main problem is not the stacking but embedded software that optimizes them.
With so much die stacking being used in mobiles, it seems inevitable that at some point, it will be easier to "push a process node" by stacking rather than shrinking. The question is when. The question is how it will be architectured. seem like keeping pieces in testable slabs makes the most sense. Will it make sense to bring BIST engines as a separate slab or stack a separate layer to handle this...