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bobdvb
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FPGA coprocessing
bobdvb   7/3/2013 7:49:45 AM
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I really want to see hybrid chips like Zynq get somewhere in the market, but the flexibility needs to be more accessible. I would like to see something along the lines of an FPGA JIT, where the OS on the fixed CPU recognises it is doing something difficult and automatically programmes a segment of the FPGA to offload that task. Think back to the transputer concepts of the 80s, well we are now doing this in software with JIT optimisation of code but we should push some of that back down to the hardware. I can foresee a JIT which reprogrammes an FPGA, I just can't make it happen.

almaktabi
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Re: FPGA coprocessing
almaktabi   7/6/2013 4:51:50 AM
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Here is a link from Microsoft Reseach describing how to do what you want...

http://research.microsoft.com/apps/video/default.aspx?id=103616

luting
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Interesting idea but not sure will fly
luting   7/3/2013 12:11:08 PM
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I don't have high confidence on this type of architecture for following reasons:

1. Hard to leverage existing eco system: Compiler, Debug, library, etc

2. Hard to expect SW engineer to write a program leverage such architecture efficienctly

3. With Program SoC from Xilinx and Altera in market, there is not enough market space left for such ideal to grow



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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