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krisi
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Re: power savings?
krisi   7/12/2013 10:54:14 AM
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Every CMOS design has different transistor sizes (W and L)...what I thought you mean by your comment was that minimum channel length in both cores is different, and that surprised me

Warren3
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Re: power savings?
Warren3   7/11/2013 7:47:29 PM
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Nope. Transistors designed to be high performance tend to be large and leaky while those designed for low power tend towards low capacitance (small self-size, small distances and gates to drive) and lowest possible leakage. 

krisi
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Re: power savings?
krisi   7/8/2013 12:26:13 PM
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different transistor sizes for both cores??? why? it is not like one is analog and the other digital

Sheetal.Pandey
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Re: power savings?
Sheetal.Pandey   7/8/2013 6:59:06 AM
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Its great to see Fujitsu is bringing something interesting on the table. Performance and power has been always contesting factors in chip development.

Warren3
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CEO
Re: power savings?
Warren3   7/7/2013 11:57:37 PM
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[Responding to Krisi 7/3 6:00 posting] Transistor sizing choices and flop staging choices would suggest not mixing the cores together. Maybe even regionalized process applications could be made? Merging of cores [also] feels like it goes counter to SOC design phylosophy generally.

krisi
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CEO
Re: power savings?
krisi   7/4/2013 11:57:21 AM
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thank you Max...I have the same impression, for this to make sense both processors have to be integrated on one die...otherwise chip to chip IO communications will negate most of the gains...Kris

Max The Magnificent
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Re: power savings?
Max The Magnificent   7/4/2013 11:38:33 AM
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@krisi: why not integrate the two dice into one big+ device?

I may be wrong, but I thought the idea was to build an SoC using the two Big-Little processors on the same die -- I don't recall hearing about them being presented on seperate dice.

krisi
User Rank
CEO
Re: power savings?
krisi   7/4/2013 9:59:13 AM
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thank you Olaf...that makes sense

Peter Clarke
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Re: power savings?
Peter Clarke   7/4/2013 6:30:43 AM
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Yes

This only applies to the SoC.

What is being compared is a Cortex-A15 core against a big-little combination of Cortex-A15-plus-Cortex A7. Or more likely four Cortex-A15s against a 4 plus 4 design.

The A15 provides high single-thread performance but burns a lot more power while the A7 is optimized for power consumption but only achieves about one third of the peak performance at about one quarter of the power consumption.

According to information shown to me by ARM: when working on a mix of Bbench web browsing benchmark plus mp3 audio streaming on a 4+4 system, big-little saves about 50 percent of the energy compared with four Cortex-A15s at the same performance level.

Where a low-level load such as MP3 playback alone does not need to wake up the Cortex-A15 at all, the energy used can be one quarter of that on an A15, In other words a big-little energy saving of 75 percent.

 

 

 

 

 

 

 

 

 

 

Olaf Barheine
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Rookie
Re: power savings?
Olaf Barheine   7/4/2013 2:47:20 AM
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I believe with 70% they mean only the power consumption of their micro-controller. But for example in a tablet computer for industrial applications the display and other parts like SSDs or WLAN controllers need the most electric power. In other words: It is just marketing.

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