Nope. Transistors designed to be high performance tend to be large and leaky while those designed for low power tend towards low capacitance (small self-size, small distances and gates to drive) and lowest possible leakage.
[Responding to Krisi 7/3 6:00 posting] Transistor sizing choices and flop staging choices would suggest not mixing the cores together. Maybe even regionalized process applications could be made? Merging of cores [also] feels like it goes counter to SOC design phylosophy generally.
What is being compared is a Cortex-A15 core against a big-little combination of Cortex-A15-plus-Cortex A7. Or more likely four Cortex-A15s against a 4 plus 4 design.
The A15 provides high single-thread performance but burns a lot more power while the A7 is optimized for power consumption but only achieves about one third of the peak performance at about one quarter of the power consumption.
According to information shown to me by ARM: when working on a mix of Bbench web browsing benchmark plus mp3 audio streaming on a 4+4 system, big-little saves about 50 percent of the energy compared with four Cortex-A15s at the same performance level.
Where a low-level load such as MP3 playback alone does not need to wake up the Cortex-A15 at all, the energy used can be one quarter of that on an A15, In other words a big-little energy saving of 75 percent.
I believe with 70% they mean only the power consumption of their micro-controller. But for example in a tablet computer for industrial applications the display and other parts like SSDs or WLAN controllers need the most electric power. In other words: It is just marketing.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.