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sanjay.churiwala
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Re: Help
sanjay.churiwala   7/14/2013 8:56:02 AM
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Hi Michael:

In terms of using names such that wildcarding could be easier: We've not covered in this book.

Implementation tools (synthesis+other optimization tools) keep on changing names of signals (e.g. during register inference/duplication etc.).

SDC does not decide the naming. Rather, SDC gets impacted by the names that a specific set of tools will choose.

Unfortuantely, each tool has its own naming convention. However, being pure technologists, both me and Sridhar wanted the book to be strictly technical only, rather than talk about any specific tool.

Regards,

sanjay

 

 

BrianBailey
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Re: Help
BrianBailey   7/11/2013 4:58:13 PM
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They did have some recommendations about naming so that things can be composed hierarchically without having to go back and change things.

Michael Dunn
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Re: Help
Michael Dunn   7/11/2013 4:45:40 PM
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Is there anything in the book about naming conventions? 

I'm recalling Altera's total disregard of system issues, but I did get the impression that with intelligent naming of signals, one's job might be greatly simplified through the magic of wildcards... Maybe. My brain just shut down, and I was fortunately able to keep using the classic timing analyzer. Might not be so lucky next time.

BrianBailey
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Re: Help
BrianBailey   7/11/2013 3:49:50 PM
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@Michael - I hear what you are saying and as I was reading the book I found myself asking - isn't there a better way to do this. However, that is the very question I should be asking if I were still an EDA tool developer, but as writers of a book they are attempting to help the people who have to use the system that is in place. So - is the book that long because they move too slowly or is the book that long because that is the mess that engineers have to deal with and they are trying to help them navigate. I think it is more of the latter.

Michael Dunn
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Michael Dunn   7/11/2013 12:02:06 PM
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I've been doing digital design for 30+ years, but have never been so confused as when I encountered SDC via Altera Quartus.

Confusion stemmed from top as well as bottom. At the system level, I found it impossible to grasp what was required in a complex design. I've got a bunch of my own HDL, a piece of 3rd-party IP, and a few Altera IP blocks in a design. Now what?

At the bottom, the docs just couldn't seem to explain what it all meant. A very simple concept that should have taken one page to explain was spread out over ten pages! A strange case of OVER-documentation that ended up losing the simple point it was trying to make in a tangle of pointless verbiage and formulae.

I've yet to look at Xilinx's Vivado dox to see if they explain SDC understandably.

Looking at this book's chapters, I wonder if it doesn't fall into the same traps. I mean...253 pages to explain basic timing specifications? What's wrong with this picture? Is the emperor naked?



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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