Tom, it is interesting that the subjects of the papers presented at the recent NV Workshop 2013, Monterey, CA, exactly match and reflect Doug Wong and Toshiba's views, with the same three front runners. The breakdown was as follows:-Flash 42.5%, ReRAM 30%, MRAM 12%, PCM 5%, CbRAM 5%, FeRAM 2.5% and memory architecture 2.5%. I included a graphical anaysis of this in the conclusion of Part 2 of my paper on IBM's latest MLC-PCM results. Part 1 of which you will find in EETimes memory section. Always remember the real picture of the future of NV memory is made from many "bits" of "multi-level" and "multi-dimensional" information.
The 3D NAND is multiple layers on same piece of silicon sharing same charge trapping layer. Of course under Coulomb repulsion, the charges may hop to next location, so retention still needs improvement.
Ron: I'd be surprised if Toshiba is ruling those out. My take was that, in this limited space, Wong didn't get to go into everything on the drawing board. But, yes, I'd be interested in hearing his take on those, too.
Doug Wong and Toshiba have 3D-NAND and ReRAM as their non-volatile (NV) memory front runners with MRAM also in the race, with respect to the potential to meet future scaling and write/erase endurance requirements. It would be nice to have heard Doug Wong's considered technical view of why phase-change memory (PCM), ferroelectric FeRAM and CbRAM are not on his or Toshiba's memory list. Should the omission of those latter three technologies from his answers be interpreted as a view that those technologies do not have the potential to scale or meet endurance requirements, or are their other technical reasons why they are not on the list?
The idea of 3D NAND is truly exciting in its potential to blow current performance levels out of the water. I'd be really interested to hear how it would be manufactured, and whether such memory would be, essentially, a cube of current 2D displays, or perhaps in a different shape -- it could be spherical, for example, if that would offer any performance enhancement. Does anyone know the answer to either question?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.