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Peter Clarke
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Re: lowest cost?
Peter Clarke   7/17/2013 10:46:50 AM
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Well Intel has indicated that they  believe 10-nm is the last node for planar NAND flash memory  but they will engineer 3D-NAND with a 40-nm minimum geometry in parallel with the 16-nm NAND generation.

 

We will see

goafrit
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Re: Blowing past Toshiba/SanDisk
goafrit   7/17/2013 10:46:19 AM
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Is the innovation in feature size or crafting better circuit architectures? 16nm can help pack more memory in small space which is good but sooner or later we just have to redesign the foundation of transistor to make real progress. After 16nm, maybe 11nm and then we are cut-off with quantum mechanical effects to go lower.

resistion
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Re: lowest cost?
resistion   7/17/2013 10:28:47 AM
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This process should be good down to 9-10 nm. Would transistors even work that small?

elctrnx_lyf
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Re: lowest cost?
elctrnx_lyf   7/17/2013 6:30:24 AM
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Hopefully the SSD's will become much cheaper in the future.

resistion
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Re: lowest cost?
resistion   7/16/2013 9:33:34 PM
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It's pitch quartering by sidewall spacer processing, not four exposures. SK Hynix showed it as well at IEDM 2011.

mcgrathdylan
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Re: lowest cost?
mcgrathdylan   7/16/2013 8:20:24 PM
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@resistion- do you think they had to use quadruple patterning to make this part? I have not had any indication that that is the case. I can look into it.

resistion
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lowest cost?
resistion   7/16/2013 7:04:36 PM
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With quadruple patterning? Figure they need to approach 10 nm to be more cost-effective.

Tom Murphy
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Re: Not that long ago
Tom Murphy   7/16/2013 4:45:23 PM
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Tom Mariner:  You're not along, my friend.  I remember those days all too well.  I even remember when we talked about sub-micron as a futuristic goal!

franzChen
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Impressive
franzChen   7/16/2013 2:49:09 PM
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It's by QP? How is the die size compared to Samsung's TLC 128Gb NAND?

Tom Mariner
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Not that long ago
Tom Mariner   7/16/2013 2:13:44 PM
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Thanks guys for making me feel old! It seems like not that long ago that I was in the Boise Micron plant watching the boats of wafers float overhead and hearing the brags of the engineers that they were "sub micron".

But I am that old -- I can remember us repairing mask or design defects so we could test by "smushing" traces together or apart with a probe needle viewed through an optical microscope.

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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