Herb, thanks for a nice writeup! I could not attend this year so your article and your valued insights as a 3D expert more than compensates for my absence there!
Your comment "IC industry will bifurcate in the near future into those pursuing Moore's Law and those pursuing "More than Moore" is quite interesting. It would seem a majority of the players will be forced in to the latter category since the costs of staying with Moore's law may be prohibitive for the new entries & smaller companies.
" same old same old ... " !! With such pollyannaish coverage, I am afraid that TSVs will remain the next hot interconnect tech even 5 years from now !
To provide a counter-point to all this happy talk, SemiCon had invited me to lead a 1 hr discussion at the Show on "Roadmap for TSVs and Alternatives from a Technology perspective ". Since Herb was not there, here are the key points :
1. unlike previous Advanced Packaging technologies like Flip Chip which we developed at IDMs like Motorola & Intel with both deep / broad expertise and product commitments, the development of TSVs has been going on mostly at overseas Govt. funded Laboratories in fits and starts and has then jumped to Foundries / OSATs. Xilinx' use of 2.5-d to integrate poorly yielding FPGAs has led to much irrational exuberance and then disappointment.
2. In the Winter of 2010 - 11 Samsung reported the first Wide I/O DRAM stack using TSVs. Great bandwidth even at 200 MHz & terrific power eff. But what the blogosphere neglected to report was that the yields were down in the mud and since then not much has been heard about Wide I/O from Samsung. Instead they keep bringing out conventional LP DDR at ever higher Clock Rates. JEDEC has actually postponed Wide I/O to 2015.
3. The development of TSV technology has been going on in Fabs who do not have to be sensitive to stress issues common in "thick film" type laminates / composites as is the case for filled vias. It is only now that they are waking up to it. Stress effects depend on the sq. of via dia., hence the new interest in shrinking them below 5 um. But integration & reliability problems ( at high Aspect Ratios both get worse ) have not been thought through. Moreover, Bonding stacked chips using the current method ( a sort of pidgin version of the technology I had invented nearly 20 years ago at Motorola for GaAs Power Amps that went into Cell Phones ) also introduces residual stress, affects electron mobility and shifts timing.
4. While these slow-poke Govt. funded Euro Labs rediscover stress effects on device perf. and the perils of Cu metallurgy applied indiscriminately, there is at least one small Company outside Chicago that has already shifted to the non - obvious ( at least to these TSV-niks ) yet theoretically sound choice of using Tungsten ( a brittle and poor electrical conductor which can be compensated by Design but unlike Cu a close CTE match with Si ).
5. But thats not all Folks - this tiny Co. with just 3 PhDs and Physicists has also solved the biggest TSV integration problem thats keeping all these Labs and various Tool Vendors new to the game ( in Herb's Osterreich they love to build big complex "Maschine" - Physics be damned ) -- intent on optimizing their individual process steps ( e,g. back up wafer bond / debond ) at the risk of compromising the whole process -- awake at night.
6. We did cover more, e,g. as to how to get the electrical benefits of TSVs w/o actually having to drill holes in live Silicon, circuitry and packages that make it possible. We already have some of these Alternatives ( using the concept of Active Interconnects ) under development - especially for the very large Server & SmartPhone markets - and have started publishing.
7. TSV development is orders of magnitude more complex than Flip Chip and would benefit from the same type of brutal, theory-driven Program Management practiced at the world's largest semiconductor Co., but since they have money in the Bank to stay on Moore's Law and thus continue single chip solutions they don't need TSVs that badly. So unless there is a radical shake - up in the TSV programs "outside", incl. at the Foundries, the present slow pace of TSV development will persist.
Morale : give TSVs a fair chance, they need a respite from these overly enthusiastic bloggers, embarassingly out of their depth, and at Conferences lets not blather about Supply Chain Issues, the technical probems are not all solved yet
@Peter, I think you can fearlessly say the word Tezzaron for Tungsten welding expertise! But in all fairness, we need to give small companies credit for taking the risk to advance 3D technologies that were hitherto the domains of big ones like Intel, Micron & IBM etc.
@Chipmonk0: I should have put "Tungsten wielding" in quotes -was meant to be a pun on Peter's comment! And there was a typo! Tezzaron does use Tungsten TSV's in the "FaStack Stacking Technology." Tungsten acts as a good stress-relieving conduit for thermo-mechanical forces.
FYI it is not possible to bond ( / "weld" ) one Tungsten filled via directly to another in the next die stacked on top. At least not at any acceptable temperature anyway. So another layer of metal has to be deposited first to cap the W vias. Then these cap layers are CMPed, and whats really great, instead of using traditional metallurgical bonding that require high temperature ( 250 C ) and pressure, are bonded at quite low temperatures in which electrons are actually shared between atoms across the interface. Co-valent bonds develop and Van der Waals forces contribute to bond strength. There are a lot of tricks in the CMP step but its Good Science overall and reduces residual stress in the stack !
As to your "wield" getting misinterpreted by another poster as "weld", in this case two wrongs ( his typo & my responding to his post ) certainly made one right. Because as explained above "weld" is relevant in the case of die stacking.
And now I shall retire to my "weald", to use an old Anglo Saxon term
Several thermal solutions using very different aproaches are under development / being implemented at Micron and IBM / 3M. The real barrier is very involved process, low yield & high cost. Simplifications / modifications to the current industry process flow along the lines of my original post are sorely needed.
@chipmonk0: yes you covered a lot more. A current thinking was 2.5 D (which is really 2D w/TSV interposer) can avoid the thermals initially. But even this may not work with SOI chips, though that's another story entirely.
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