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DrFPGA
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Re: How About A Chess Playing Super Computer?
DrFPGA   7/25/2013 12:13:44 PM
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Peter-

Chess algorithms are usually tuned to the targeted hardware and use various 'tricks' (like using 64-bit board representations that can be managed and operated on easily by 64-bit procesors). Having ranks of processors could allow new algorithms to emerge that might identify ways to use very massive processor banks for a variety of algorithms: physical systems that are currently difficult to model (EM fields, turbulent fluid flow, large molecule interactions, encryption/decryption, etc.)

DrFPGA
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Re: How About A Chess Playing Super Computer?
DrFPGA   7/25/2013 12:07:51 PM
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On practical advantage is a better understanding of how to break algorithms into pieces that can be efficiently executed on a large number of processors. Chess computers uses algorithms that are common to other difficult problems (economics, scheduling, FPGA routing, etc) so this could help identify some new algorithmic approaches to solving other problems.

rich.pell
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Re: How About A Chess Playing Super Computer?
rich.pell   7/25/2013 7:28:44 AM
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Are there any practical advantages to developing a more advanced chess playing algorithm/computer? 

rich.pell
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Re: Cheap Firepower
rich.pell   7/25/2013 7:19:48 AM
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"What would people use this for?"

While it's certainly interesting to speculate on the potential applications, I'm reminded of similar questions about the neverending increase in disk storage capacity.  It seems like a case of "build it and they [applications] will come."

Peter Clarke
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Re: How About A Chess Playing Super Computer?
Peter Clarke   7/25/2013 6:52:44 AM
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Isnt it as much about the solution algorithm as the computational resources?

My understanding is that successful chess playing machines use a mix of deep move calculation and mapping more abstract ideas to successful chess playing.

 

 

p_g
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amazing...
p_g   7/25/2013 4:51:30 AM
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50Gflops/watt ?? waiting to see how this core making into mobile devices giving them amazing compute power for gaming....

DrFPGA
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How About A Chess Playing Super Computer?
DrFPGA   7/25/2013 12:35:27 AM
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I'd like to see stacks of these implement a distributed chess playing algorithm to create the best chess playing computer in the world. It would crush every existing chess computer out ther. After we do that we would move on to predicting the weather...

Anyone interested in helping to make it happen?

zhgreader
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Re: eLink
zhgreader   7/24/2013 10:35:31 PM
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this may change the current desktop concept. farmwork.

mlloyd
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Re: eLink
mlloyd   7/24/2013 2:28:17 PM
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Source synchronous LVDS -- that would be great for a robust, versitile interface.  8 data lanes is not too many pins compared to the much lower bandwidth parallel interfaces we have used to communicate with processors currently available on the market.  Thanks for the information!  I hope to have the opportunity to use the Parallella.

adapteva
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Re: Thanks!
adapteva   7/24/2013 1:43:27 PM
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Definitely! We might even post a construction video.

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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