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JanineLove
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One Environment to Test Them All
JanineLove   7/24/2013 2:54:36 PM
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What are the stoppers/challenges for addressing structural, functional and performance issues in one environment?

SrivRagh
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Re: One Environment to Test Them All
SrivRagh   7/25/2013 8:14:47 AM
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Hi Janine,
    I am assuming that you are referring to different simulation platforms (like virtual-prototype, RTL simulator or emulators like Palladium) when you use the word "environment". These platforms provide different levels of observability and simulation-performance (sim-performance) throughput. For example: RTL simulators give better observability but low sim-performance while emulators give marginal observability but deliver on sim-performance. Depending upon the verification stage, platforms are chosen, for example initially RTL simulator is chosen as the scenarios one would run are simple and the expectation is more bugs will be flushed out at this stage. But when confidence on RTL is built, folks take it to emulation or Sim-accelerators for stress testing and benchmarking.
Presently emulation vendors are improving observability and investing on transactional VIPs (partly synthesize-able) to re-use test-bench. My take, emulation platform may be the way to go but bottlenecks like compilation, cost etc will have to be addressed before it is adopted widely.


Thx
Srivats

Peter Clarke
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Re: One Environment to Test Them All
Peter Clarke   7/25/2013 11:01:06 AM
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As with many things there is a trade off.

You can verify fairly completely at a high-level of abstraction OR you can verify special corner cases in detail down to the metal.

But quite understandably in terms of the energy required no-one has found a way to verify completely, across the piece AND in detail.

So bugs can still creep through.

The challenge is where to put the effort in terms of improving the various forms of verification tool...virtual-prototype platform, RTL simulator and hardware-driven emulator.

Right now the empasis appears to be on the new kid on the block, virtual prototyping in sofware running on high-speed models.

 

 

 

 

 

 

 

narasimh
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Comments : Let's Get System-Level Functional Verification Under Control
narasimh   2/6/2014 1:54:28 AM
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Few comments:


1. Typically SoC platform from companies have derivative platforms with some features added or removed. There seems to be redundancies/duplication of efforts in functional verification in these kind of scenarious which is potential areas for savings.

2. Placing higher priority to VP platform for system level verification makes sense. Getting software run on VP without issues can ensure lot of success to business. Key reason being time to market. Software stack is critically tested on VP, and running on hardware ensures minimal software issues.

3 If the software use/test case can capture details of the the components, registers, memory sections... from the entire state space that are activated, one can gain higher level of confidence in verifcation.



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