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Max The Magnificent
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Triple Lock-Stepped CPUs?
Max The Magnificent   7/31/2013 3:40:25 PM
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Rather than use dual lock-step CPUs and have an error cause a halt or a reset, are there any MCUs with triple lock-step CPUs with voting such tha tan error doesn;t cause the system to slow?

Max The Magnificent
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Marching in lock-step
Max The Magnificent   7/31/2013 3:41:42 PM
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One can assume a lot from the term "lock step" ... but assumptions are often incorrect. Can you summerize what lock-step actually entails?

Max The Magnificent
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Hard or Soft
Max The Magnificent   7/31/2013 3:44:52 PM
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Some MCUs have dual processors that boast a hard lock-step capability.

What about MCUs with dual processors that don't support hard lock-step ... one hears the term "soft lock-step" ... shat is this and how does it compare to its hard counterpart?

wmwmurray01
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Re: Triple Lock-Stepped CPUs?
wmwmurray01   8/1/2013 5:29:26 PM
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Max -- Believe the Space Shuttle Computers actually used 3 voting, and one hot spare, plus a tertiary back up.

 

This is pretty interesting for a sub $10 part, as it gives one a safety certified CPU / OS / and Tools at quite a reasonable price (Heaven Knows Cars are Expensive These days)  Speed is up to 180MHZ for an ARM R4 Core with Floating Point, so it should offer enough Zip to do many of the calculations to do things like boost fuel economy, cut emissions, etc)

 

For many applications one just wants to detect a fault and restart / halt -- as one may not know if a mechanical fault(most common at the system level), power supply fault(most common electrical), or some other fault has happened.

(Obvious you have not done much work on your own car, or gotten into a helicopter you have had to help work on, and head up a mountain)

wmwmurray01
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Re: Hard or Soft
wmwmurray01   8/2/2013 3:42:02 PM
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Believe in one (Hard) the operations in the two CPU's occur at the same time, in Soft there is a Time Delay (to prevent a common error, such as power rail noise, or ionizing radiation, or other error(soft or hard) from producing incorrect results.  (Lockstep refered originally to prisoners marching at close interval)(In the Royal Marine's this was known as Half-Interval March)

DrFPGA
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Multiple Implementations- Different Designs
DrFPGA   8/6/2013 10:03:41 AM
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Another approach to reliability is to implement the application with two different types of designs. You can have different programmers implement the design differently and this reduces the possibility of a software bug failing in the same way when a single deisgn is just copied to two CPUs. Another approach is to use a different technology (perhaps an FPGA) to implement the second design. This reduces the chance of a bug showing up in both implementations at the same time even more.

Max The Magnificent
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Re: Triple Lock-Stepped CPUs?
Max The Magnificent   8/7/2013 10:32:01 AM
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@wmwmurray01: Obvious you have not done much work on your own car, or gotten into a helicopter you have had to help work on, and head up a mountain


Guilty as charged -- cars are one of those things that I understand theoretically -- but don;t have a clue what I'm duing when I'm lying underneath one with oil dripping on my head from the big watchmacallit next to the doohickey

Max The Magnificent
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Re: Multiple Implementations- Different Designs
Max The Magnificent   8/7/2013 10:33:47 AM
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@DrFPGA: Another approach to reliability is to implement the application with two different types of designs...

Isn't this scalled somrething like "Design Diversity" as opposed to "Design Redundancy"?

DrFPGA
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Re: Multiple Implementations- Different Designs
DrFPGA   8/7/2013 11:37:27 AM
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Max- Yep, Design Diversity is the common term used to describe a design with two different implementations using two different technologies.

Max The Magnificent
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Re: Multiple Implementations- Different Designs
Max The Magnificent   8/7/2013 11:39:10 AM
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@DrFPGA: Max- Yep, Design Diversity is the common term used to describe...


Ha! I'm not as stupid as I look (but then again, how could I be? :-)

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