Resistion: I think using any mechanism it is always possiblel to build a bridge and then rupture it in a fuse like manner. As long as the rupture is not too violent and the atoms stay nearby then the mechanism that created the link can be used to suck them back in. I think this would offer a means of making a uni-directional device.
Or it could be that the position of the link moves to a new location, OK if you have a large area device, you might run into a few write/erase lifetime problems when you try to scale to sub 20nm. I think in the past many of the so called memory devices based on aluminium oxide utilized this moving filament mechanism.
I know from my own experience with lateral nichrome fuses for PROMs when you try and lithographically scale them you will find that the fused devices will relink after many hours of operation with applied fields. Something to do with ion movement in the dielectrics and that is why the vertical fused PROM and the antifuze was developed.
The only caveat I might raise there is that when flash memory involves a new memory cell structure....and even old resistence change mechanisms at new geometries....doesn't that need stringent reliability data too.
Just because something worked reliably at 90-nm and 50-nm doesn't mean it will at 19-nm and 16-nm.
For a start NAND flash cycling endurance is reducing rapidly
And different unintended consequences could be coming into play at each node.
There will be very thin layers of silver so expense should not be an issue.
There could be different bit-line electrodes above a cell sized area of silver, to further reduce the amount of silver in use.
The issue it more likely to be the concerns about using silver and contamination of equipment. These would be similar concerns to those about copper, which had to be overcome for the use of copper in IC interconnect
Dr FPGA The technology will stand or fall based on reliability test results. Yes years are needed, but I think very large numbers of devices and memory arrays tested will be a good substitute. The results must be backed up by the exact numbers of devices tested with the exact details of the test conditions under which they were tested and the failure anaysis. The problem is without read verify after every write/erase operation it is possible for devices of this type to undergo write fail-repair cycles with the result that in a free running w/e test the device appears to be operating normally many cycles after a failure would have been recorded in the a real world application. This can lead to erroneous claims of long intrinsic write/erase lifetimes with the problem that those numbers are never achieved with real products. In those cases the definition of intrinsic lifetime appears to be the lifetime achieved once when the claiment was not too careful with the test conditions. Lets hope Crossbar will avoid those pitfalls.
The existing technologies aren't that reliable. Sure you have to test reliability with best effort but it's always subject to challenges and customer paranoia. Freescale gets a lot of automotive electronics parts returns from "paranoid" customers. Generates good reliability statistics.
The papers by the developers Sung Hyun Jo and Wei Lu indicated bidirectional switching, rather than using one direction. Ag filaments are formed, though claimed not in the sense of electroplating or "programmable metallization" of the counterelectrode. But even the CBRAM guys have reported unidirectional switching which might be diode-compatible.
But at least for me, it's 'CBRAM' if the source of the filament is one of the electrodes.
Resistion: I think the difference is the Adesto device is really a solid state electrochemical plating cell, in that ions must be moving in both directions. In the Crossbar memory I am not aware that anything happens other than silver ions move through the a-SiH matrix. Silver is a fast diffuser and in the presence of high field and hydrogen can most likely move easily backwards and forwards through the matrix. The process is perhaps more akin to an electromigration like effect than plating.
A more interesting question is does the filamant actually completely bridge the inter-electrode gap or does it stop short with a tunnelling gap completing the link.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.