Assuming the 24 levels maximum, and a F=50 nm 6F^2 design rule, the maximum 3D density is equivalent to a conventional 12.5 nm floating gate. So the density lead for this case is temporary, until someone (if anyone) hits 10 nm floating gate. Increasing the number of levels or shrinking the 3D NAND design rule could increase costs when the number of steps starts multiplying, e.g., doubling.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.