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resistion
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Delay?
resistion   4/19/2014 8:55:33 PM
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chipmonk0
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Re: Stacked 3d package for stacked NAND chips
chipmonk0   8/8/2013 11:33:10 AM
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@Peter Clarke : Thx in advance.

pseudoid
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Baby Steps
pseudoid   8/7/2013 3:43:56 PM
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Our industry needs to continue with attempts to never make our esteemed colleague Gordon E. More wrong! 

I know we are getting there in small baby steps, including the eventuality of 3D fab. 

At the current time, the bottleneck appears to be with the copper interconnects (physical throughput speed limit).  I can't wait for the day when finally Samsung and Intel cross paths at match.com and start courting each other.  "Hello 3D NAND! Please meet Silicon Photonic ICs." ;)

"We have been developing process technology to create a monolithic, photonic sub-system. We build these just like you build any other kind of IC, in a standard chip factory," states Intel's Rattner

Pasted from <http://www.electronicsnews.com.au/features/what-bottleneck-silicon-photonics-technology-boost>

krisi
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how many electrons?
krisi   8/7/2013 3:23:09 PM
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The article states that the new memory cell relies of electron trapping. So how many electrons are trapped to store 1? Can anyone offer an educated guess? Kris

any1
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Re: 2 Questions
any1   8/7/2013 1:41:23 PM
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This is an interesting development. I think it is likely that Samsung knows, along with every other major player in the memory business, that 3D NAND is just a question of when not if.  Then, it may make sense to get some early learning on volume manufacturing of this technology a node or two ahead of when you think you will actually need it.  You can do all of the modeling of cost, device physics, processing, etc.  But until you actually do it on a higher volume basis you really don't know what you don't know.

So I would call 3D NAND a "More than Moore" approach since the minimum feature size is actually getting larger.  It only makes sense if it produces a better device at a lower cost than the 2D equivalent.  And this remains to be determined.

Peter Clarke
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Re: Stacked 3d package for stacked NAND chips
Peter Clarke   8/7/2013 1:39:45 PM
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I'll ask Samsung

 

 

Peter Clarke
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Re: 2 Questions
Peter Clarke   8/7/2013 1:38:52 PM
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1) 1 byte = 8 bits so, yes, 128-Gbit = 16-Gbyte

It ihas been the convention within the semiconductor industry to quote memory capacity in bits. But either bits or bytes will do.

2) By which i mean planar scaling has become moot with regards to scaling memory capacity

 

 

 

pseudoid
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2 Questions
pseudoid   8/7/2013 12:46:18 PM
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1)  I am slightly confused about the wordage "128 Gbit V-NAND" CTF:  Would that be the equivalent of 16GByte memory, or is this going to be a new unit of measure?

2) Does this news also mean that "Moore's Law" has been removed from its premature life support systems?

chipmonk0
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Stacked 3d package for stacked NAND chips
chipmonk0   8/7/2013 12:31:22 PM
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Read in a blog somewhere that Samsung is going to sell their 3d NAND in a 128 GB configuration by stacking 8 chips vertically and connecting them with TSVs ( Through Silicon Vias ). Can Peter Clarke or anyone else comment on this ?

resistion
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Re: max density
resistion   8/6/2013 7:59:14 PM
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Assuming the 24 levels maximum, and a F=50 nm 6F^2 design rule, the maximum 3D density is equivalent to a conventional 12.5 nm floating gate. So the density lead for this case is temporary, until someone (if anyone) hits 10 nm floating gate. Increasing the number of levels or shrinking the 3D NAND design rule could increase costs when the number of steps starts multiplying, e.g., doubling.

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