Assuming the 24 levels maximum, and a F=50 nm 6F^2 design rule, the maximum 3D density is equivalent to a conventional 12.5 nm floating gate. So the density lead for this case is temporary, until someone (if anyone) hits 10 nm floating gate. Increasing the number of levels or shrinking the 3D NAND design rule could increase costs when the number of steps starts multiplying, e.g., doubling.
Read in a blog somewhere that Samsung is going to sell their 3d NAND in a 128 GB configuration by stacking 8 chips vertically and connecting them with TSVs ( Through Silicon Vias ). Can Peter Clarke or anyone else comment on this ?
NASA's Orion Flight Software Production Systems Manager Darrel G. Raines joins Planet Analog Editor Steve Taranovich and Embedded.com Editor Max Maxfield to talk about embedded flight software used in Orion Spacecraft, part of NASA's Mars mission. Live radio show and live chat. Get your questions ready.
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