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any1
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Re: 2 Questions
any1   8/7/2013 1:41:23 PM
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This is an interesting development. I think it is likely that Samsung knows, along with every other major player in the memory business, that 3D NAND is just a question of when not if.  Then, it may make sense to get some early learning on volume manufacturing of this technology a node or two ahead of when you think you will actually need it.  You can do all of the modeling of cost, device physics, processing, etc.  But until you actually do it on a higher volume basis you really don't know what you don't know.

So I would call 3D NAND a "More than Moore" approach since the minimum feature size is actually getting larger.  It only makes sense if it produces a better device at a lower cost than the 2D equivalent.  And this remains to be determined.

krisi
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how many electrons?
krisi   8/7/2013 3:23:09 PM
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The article states that the new memory cell relies of electron trapping. So how many electrons are trapped to store 1? Can anyone offer an educated guess? Kris

pseudoid
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Baby Steps
pseudoid   8/7/2013 3:43:56 PM
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Our industry needs to continue with attempts to never make our esteemed colleague Gordon E. More wrong! 

I know we are getting there in small baby steps, including the eventuality of 3D fab. 

At the current time, the bottleneck appears to be with the copper interconnects (physical throughput speed limit).  I can't wait for the day when finally Samsung and Intel cross paths at match.com and start courting each other.  "Hello 3D NAND! Please meet Silicon Photonic ICs." ;)

"We have been developing process technology to create a monolithic, photonic sub-system. We build these just like you build any other kind of IC, in a standard chip factory," states Intel's Rattner

Pasted from <http://www.electronicsnews.com.au/features/what-bottleneck-silicon-photonics-technology-boost>

chipmonk0
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Re: Stacked 3d package for stacked NAND chips
chipmonk0   8/8/2013 11:33:10 AM
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@Peter Clarke : Thx in advance.

resistion
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Delay?
resistion   4/19/2014 8:55:33 PM
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resistion
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Re: 3D NAND Delay?
resistion   4/20/2014 8:28:02 PM
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Samsung seems to have already made a statement 2/17 that they are working on 32 layers (at once I presume), but they have no issues with 24 layers. Indeed, they need to be able to do 32 or more layers at once if possible, to keep the scalability advantage.

http://m.hankyung.com/apps/english.view?aid=201402172111041

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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