Assuming the 24 levels maximum, and a F=50 nm 6F^2 design rule, the maximum 3D density is equivalent to a conventional 12.5 nm floating gate. So the density lead for this case is temporary, until someone (if anyone) hits 10 nm floating gate. Increasing the number of levels or shrinking the 3D NAND design rule could increase costs when the number of steps starts multiplying, e.g., doubling.
Read in a blog somewhere that Samsung is going to sell their 3d NAND in a 128 GB configuration by stacking 8 chips vertically and connecting them with TSVs ( Through Silicon Vias ). Can Peter Clarke or anyone else comment on this ?
This is an interesting development. I think it is likely that Samsung knows, along with every other major player in the memory business, that 3D NAND is just a question of when not if. Then, it may make sense to get some early learning on volume manufacturing of this technology a node or two ahead of when you think you will actually need it. You can do all of the modeling of cost, device physics, processing, etc. But until you actually do it on a higher volume basis you really don't know what you don't know.
So I would call 3D NAND a "More than Moore" approach since the minimum feature size is actually getting larger. It only makes sense if it produces a better device at a lower cost than the 2D equivalent. And this remains to be determined.
Our industry needs to continue with attempts to never make our esteemed colleague Gordon E. More wrong!
I know we are getting there in small baby steps, including the eventuality of 3D fab.
At the current time, the bottleneck appears to be with the copper interconnects (physical throughput speed limit). I can't wait for the day when finally Samsung and Intel cross paths at match.com and start courting each other. "Hello 3D NAND! Please meet Silicon Photonic ICs." ;)
"We have been developing process technology to create a monolithic, photonic sub-system. We build these just like you build any other kind of IC, in a standard chip factory," states Intel's Rattner