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soqeh
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at least 40-50 nm
soqeh   8/9/2013 1:14:16 AM
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As is well-known, in the charge-trap FLASH, an ONO triple-layer is used as a memory layer. For the V-NAND FLASH, the ONO layer is formed to cover an inner surface of a hole vertically penetrating word-line layers. Since the thickness of the ONO layer cannot be shrunk, the penetrating hole should be larger than, at least, twice of the thickness of the ONO layer. In addition, a polysilicon layer serving as a channel should be formed in the penetrating hole. This means that the design rule of the V-NAND should be larger than 50 nm. Owing to this, Samsung emphasized that there is no need for EUV.

These facts were explained by Macronix, in order to stress technical advantages of their VG-NAND type FLASH over Samsung's TCAT or Toshiba's BiCS. 

http://www.sematech.org/meetings/archives/symposia/9027/pres/Session%203/Lue_HangTing.pdf (See P. 31)

 

In conclusion, your answer of about 45nm seems to be right. However, it is uncertain whether the assumptions are right. This is because each nand string of 2D FLASH is realized on a xy plane parallel to the wafer but that of 3D V-NAND is realized on a xz or yz plane. In other words, to answer your question, additional information (e.g., on a 2D area of unit cell of 3D V-NAND) should be provided. I think that the number of the penetrating holes is directly related to this information. (Although I can't remember the exact site, I read that somewhere.)  

In the meantime, 3D RRAM may be superior to V-NAND FLASH. However, it should be emphasized that V-NAND FLASH is already in production stage. It seems that 3D RRAM is still in developing stage. 

resistion
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CEO
Re: Going deeper
resistion   8/8/2013 7:12:00 PM
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I agree with Peter's assessment. If 24 is the max, they could start SLC then go to MLC then TLC. Otherwise they'd be expected to do 48 layers next, then 96, etc. It might mean they start RRAM in 2017-2019 time frame.

Peter Clarke
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Re: Going deeper
Peter Clarke   8/8/2013 5:35:18 PM
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I have asked.

chipmonk0
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Re: Going deeper
chipmonk0   8/8/2013 11:42:03 AM
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I will ask the same questions I had earlier asked @Peter.

Per some blog Samsung is supposed to stack 8 of these 3-d NAND chips and sell them as a 128GB module. That blog claimed that the 8 chips will use TSVs for vertical interconnect. Perhaps Peter will soon have an answer from Samsung, if not could @Rick pl. ask Samsung about it at the Flash summit in SJ ?

rick merritt
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Author
Going deeper
rick merritt   8/8/2013 11:03:56 AM
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Nice job digging deeper into his vertical and somewhat foggy territory, Peter!

I understand Samsung will present at next week's Flash Summit in San Jose and I am trying to get a look sat foils to see if they will add anything to this discussion.

Meanwhile I wonder, what is the interest level in this topic in the community? Do you have specific questions about this technology? Do you care HOW it works or only that it has X, Y and Z specs and costs?

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