Thanks for pursuing the details. But for sure each of the 24 layers has its own iteration of mask redeposition (to prevent hole widening), nitride etch, and oxide etch. If applied to spacer pitch division, the pitch would have been divided by 2^24, or almost 17 million, yet for 24 layer 3D NAND, it's only effectively divided by about 5. That's the cost efficiency gap.
@rage33: it's a good consideration. Although in the TCAT the gate dielectric layers are wrapped around the gate, it may not be simple alternating of two layers.
There was a followup statement by Samsung which confirmed they were using MLC, but the 24 layers probably should be taken to mean device layers. Because in the statement they emphasized the desire to go beyond the 10 nm equivalent density. This would be possible with both MLC and 24 device layers.
They also said 24 layers, not 24 storage layers. This could mean that memory storage is only 12 layers with passivating layers between. They could be counting all the layers to total the 24.
I think we can also assume this is MLC. They claimed 35k write cycles on this and how it had 2-10X better reliability than existing NAND. Assuming this is in reference to cycling, SLC can already exceed 35k cycles.
There is some extra cost for requiring double patterning even at the looser design rule. And there are many layers to be deposited and etched which in total far exceed the material consumption by quadruple patterning. I think all that is reduced dramatically is exposure cost but they're adding new layers and are they really patterning all the 24 layers in one shot (how thick photoresist?).
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