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resistion
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vertical NAND string
resistion   9/11/2013 12:27:02 AM
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If it exceeds 64 layers, that would be a longer than standard string length that degrades performance. So not much leg here.

double-o-nothing
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Re: 3D NAND requires more than double patterning
double-o-nothing   8/21/2013 9:36:32 PM
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Etching 24 pairs of alternating layers without deposition would be sufficient for pitch/24, in alternate spacer schemes.

resistion
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Re: 3D NAND requires more than double patterning
resistion   8/21/2013 10:03:10 AM
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Thanks for pursuing the details. But for sure each of the 24 layers has its own iteration of mask redeposition (to prevent hole widening), nitride etch, and oxide etch. If applied to spacer pitch division, the pitch would have been divided by 2^24, or almost 17 million, yet for 24 layer 3D NAND, it's only effectively divided by about 5. That's the cost efficiency gap.

resistion
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Re: 3D NAND requires more than double patterning
resistion   8/21/2013 3:16:44 AM
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Not so sure about that. Check the narrowest line positions has some discontinuity. But need a better view to confirm.

soqeh
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Re: 3D NAND requires more than double patterning
soqeh   8/21/2013 2:08:47 AM
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resistion
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Re: 3D NAND requires more than double patterning
resistion   8/20/2013 9:18:11 PM
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@rage33: it's a good consideration. Although in the TCAT the gate dielectric layers are wrapped around the gate, it may not be simple alternating of two layers.

There was a followup statement by Samsung which confirmed they were using MLC, but the 24 layers probably should be taken to mean device layers. Because in the statement they emphasized the desire to go beyond the 10 nm equivalent density. This would be possible with both MLC and 24 device layers.

http://www.theregister.co.uk/2013/08/19/samsung_launches_damp_3d_ssd_squib/

But they achieve this goal at very high cost. It appears necessary they need to do at least one process sequence iteration. Thus it is targeted for enterprise rather than consumer.

http://www.engadget.com/2013/08/13/samsung-unveils-first-ssds-with-3d-v-nand-memory/

The latter announcement at engadget also confirms the 24 layers as device layers.

rage33
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Re: 3D NAND requires more than double patterning
rage33   8/15/2013 1:38:39 PM
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They also said 24 layers, not 24 storage layers.  This could mean that memory storage is only 12 layers with passivating layers between.  They could be counting all the layers to total the 24.  

I think we can also assume this is MLC.  They claimed 35k write cycles on this and how it had 2-10X better reliability than existing NAND.  Assuming this is in reference to cycling, SLC can already exceed 35k cycles.

resistion
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Re: 3D NAND requires more than double patterning
resistion   8/15/2013 10:51:58 AM
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That's a good point. Microloading or insufficient resist thickness can limit the etch depth, and therefore the number of layers. But iterating cannot reduce the cost per bit.

 

Peter Clarke
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Re: 3D NAND requires more than double patterning
Peter Clarke   8/15/2013 8:07:23 AM
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I doubt they are patterning the layers in one shot.

I am sure it is an interative process building up the layers

And then punch through with connecting via.

So I think you are right if you are implying much longer dwell-time on the exposure and etch machines to end up with 24 layers but only the same memory capacity.

But the masks are cheaper in older technology...and in theory this may scale to say 96 layers providing a memory density otherwise unachievable.

 

 

 

 

 

double-o-nothing
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3D NAND requires more than double patterning
double-o-nothing   8/15/2013 1:12:13 AM
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There is some extra cost for requiring double patterning even at the looser design rule. And there are many layers to be deposited and etched which in total far exceed the material consumption by quadruple patterning. I think all that is reduced dramatically is exposure cost but they're adding new layers and are they really patterning all the 24 layers in one shot (how thick photoresist?).

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