Nice job digging deeper into his vertical and somewhat foggy territory, Peter!
I understand Samsung will present at next week's Flash Summit in San Jose and I am trying to get a look sat foils to see if they will add anything to this discussion.
Meanwhile I wonder, what is the interest level in this topic in the community? Do you have specific questions about this technology? Do you care HOW it works or only that it has X, Y and Z specs and costs?
I will ask the same questions I had earlier asked @Peter.
Per some blog Samsung is supposed to stack 8 of these 3-d NAND chips and sell them as a 128GB module. That blog claimed that the 8 chips will use TSVs for vertical interconnect. Perhaps Peter will soon have an answer from Samsung, if not could @Rick pl. ask Samsung about it at the Flash summit in SJ ?
I agree with Peter's assessment. If 24 is the max, they could start SLC then go to MLC then TLC. Otherwise they'd be expected to do 48 layers next, then 96, etc. It might mean they start RRAM in 2017-2019 time frame.
If the technology were not at least theoretically capable of MLC, it might be hard to push. Extending vertically might be only way otherwise. It might make MLC harder by reducing read current. And there could be retention issues since there is no opportunity to confine charge vertically.
As is well-known, in the charge-trap FLASH, an ONO triple-layer is used as a memory layer. For the V-NAND FLASH, the ONO layer is formed to cover an inner surface of a hole vertically penetrating word-line layers. Since the thickness of the ONO layer cannot be shrunk, the penetrating hole should be larger than, at least, twice of the thickness of the ONO layer. In addition, a polysilicon layer serving as a channel should be formed in the penetrating hole. This means that the design rule of the V-NAND should be larger than 50 nm. Owing to this, Samsung emphasized that there is no need for EUV.
These facts were explained by Macronix, in order to stress technical advantages of their VG-NAND type FLASH over Samsung's TCAT or Toshiba's BiCS.
In conclusion, your answer of about 45nm seems to be right. However, it is uncertain whether the assumptions are right. This is because each nand string of 2D FLASH is realized on a xy plane parallel to the wafer but that of 3D V-NAND is realized on a xz or yz plane. In other words, to answer your question, additional information (e.g., on a 2D area of unit cell of 3D V-NAND) should be provided. I think that the number of the penetrating holes is directly related to this information. (Although I can't remember the exact site, I read that somewhere.)
In the meantime, 3D RRAM may be superior to V-NAND FLASH. However, it should be emphasized that V-NAND FLASH is already in production stage. It seems that 3D RRAM is still in developing stage.
There is some extra cost for requiring double patterning even at the looser design rule. And there are many layers to be deposited and etched which in total far exceed the material consumption by quadruple patterning. I think all that is reduced dramatically is exposure cost but they're adding new layers and are they really patterning all the 24 layers in one shot (how thick photoresist?).
They also said 24 layers, not 24 storage layers. This could mean that memory storage is only 12 layers with passivating layers between. They could be counting all the layers to total the 24.
I think we can also assume this is MLC. They claimed 35k write cycles on this and how it had 2-10X better reliability than existing NAND. Assuming this is in reference to cycling, SLC can already exceed 35k cycles.
@rage33: it's a good consideration. Although in the TCAT the gate dielectric layers are wrapped around the gate, it may not be simple alternating of two layers.
There was a followup statement by Samsung which confirmed they were using MLC, but the 24 layers probably should be taken to mean device layers. Because in the statement they emphasized the desire to go beyond the 10 nm equivalent density. This would be possible with both MLC and 24 device layers.
Thanks for pursuing the details. But for sure each of the 24 layers has its own iteration of mask redeposition (to prevent hole widening), nitride etch, and oxide etch. If applied to spacer pitch division, the pitch would have been divided by 2^24, or almost 17 million, yet for 24 layer 3D NAND, it's only effectively divided by about 5. That's the cost efficiency gap.
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