I have to disagree that it is not a good method after reading more papers on this topic, although some guys are using this in their papers. For example, firstly making a device 200 microns for the electrode, then 100, 50 etc.
A simple question is where is the filament? If you don't know it, changing area does not make sense. I also have many other concerns.
Several ways. First, by the obvious, that is, the device is "born on", that is, it is perfectly ohmic as made - this only happens if doped by CO. Then, by degrees of doping, being always ohmic if the higher doping level is used, and down to born insulating as doping goes to zero. Optimizing doping, allows ohmic behavior as born on down to small areas. Thus, the filament idea is more of a "soft breakdown" nature when the resistance is high due to small areas. It then became a "science" as doping is not truly understood - that is, doping here is not to change the conductivity by shifting the fermi level - instead, it is a coordination number balancing - i.e., CO is a ligand that substitutes for lost oxygen and increase of uncompensated Ni. Such ligand substitution is not what the same as doping in the semiconductor sense. That is, it is not what is usually done in the so-called "Hydrogenic doping"-e.g.,as Phosphorus in Si, donating an electron to the conduction band - here, it only adjusts Ni to have Ni(+2) to be the dominant species and be the new ground state and go unimpedent to N(+1) and Ni(+3) "disproportionation reaction" responsible for the reversible Metal/Insulator transition. With formation of filaments, we have Ni(0) and Ni(+4) which impedes reversibility, unless in an area, randomly created, where the disproportionation reaction occurs and the "reconnection" of filaments leads to a "short" or "open" circuit, which becomes the operation mode of a filament based switch. Thus, an impure and stochastic systm becomes the "memory paradigm" for filamentary ReRAMs, versus a materials design technique for CeRAM. Also, the usual cross section TEM is used to detect filaments. The Metal/insulator transition is a quantum phase transition effect in most Transition Metal Oxides, but ultra thin (60 nm) devices have lots of non-stoichimetric areas, and the optimal control of oxidation number species is impossible to control in filamentary ReRAMs. Detailed transport based on "tunneling with e-e correlations" has been published in the May 31st, 2011 issue of J. Appl. Physics. More detailed work is in press.
Our output stages are limited to 20mA and cannot be damaged by a short. However, they will be slow, generating 500ns pulses off-the-shelf. They could theoretically go to 100ns with a change in programming and some potentiometer adjustments but that is still slow for you. The existing systems are targeted at ferroelectric devices with high impedance so current resolution is excellent above 100kohm but not in the ohm range. That being said, an off-the-shelf system could program your elements and distinguish memory states. With mods, we could give you more sensitivity for the conductive state if the read pulses are kept very short. Then, with our Vision operating system already in place, you would be able to create any parameter, stress, or reliability test you wanted without our having to write custom software for you. In particular, you could easily set up tests to run fatigue, "imprint", and retention tests of your individual memory elements over temperature and voltage conditions under automated control. (I assume that these three classice ferroelectric reliability issues are present in your technology but just express themselves in a different manner.)
I do not think we would see oscillation in our test circuitry during the the metal-to-insulator transition. Mathematically, it is little different than the switching of a very square ferroelectric capacitor although the resistance range is probably several orders of magnitude higher. (Our 20/80 PZTs change effective capacitance by a factor of 100 during switching.)
As for speed, it is the same situation as with ferroelectric caps: put a memory element on a CMOS substrate to get precise pulse width control under expected operating conditions. You could inexpensively make the control dice (not full up memories) on MOSIS and then bump down your memory elements. This arrangement could get you probably to several nanoseconds with MOSIS specs. That is not femtoseconds but the resulting test data cache would be huge (necessary for statistics) and robust. We can control such a chip with our equipment so the programmability of Vision would be available immediately.
Please contact me directly, Carlos. I do not know your e-mail. Go to our web site www.ferrodevices.com and fill out a customer form. Michelle will pass it to me.
BOTH - BUT PUND in the conductive state must be done in such a way that that you do not fry the pulse generator. For materials development, we have to use the masks that are single resistors etc. In that case we have high geometry (130) and lower (30). It is necessary then to have approriate active current compliance. In the CMOS, the compliance is done with the circuit on board.
What I was interested is to see if we can get the switching speed. In some materials, lasers had to be used due to the tens of femtoseconds regime. But, we can slow it down and see if your system could be used - however, we must also thing of feedback in the compliance, since going from metal-like to insulator is not tracktable. Any thoughts on a system with feed back so that it will not oscilate.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.