@Vince: ...And just to clarify, I'm not advocating a data standard that can be used to move ALL design data and subtleties from one vendor tool to another; I'm advocating this approach as a means to import reference designs.
Some of these varying factors can be accommodated in the format by establishing a common set of elements and properties with the assistance of EDA tool vendors, and the leverage of current standards such as IPC-2581. The initiative could be further supported with a style-guide that outlines common stack-ups, conventions, etc. We're really talking about board-level IP reuse across vendor tools. I see silicon IP design reuse as very successful and it has been characterized by style-guides (Reuse Methodology Manual [RMM]), standard design definition formats (Register Transfer Logic [RTL]), syntax checkers, etc. The community could leverage some of these concepts for a workable board-level exchange standard. And just to clarify, I'm not advocating a data standard that can be used to move ALL design data and subtleties from one vendor tool to another; I'm advocating this approach as a means to import reference designs.
Vince -- I'm all in favor of having this sort of reference design -- but one thoing that worries me is the fact that different boards have different stacks (number of layers, order of layers [esp. power and ground planes], different trace widths and pad sizes and impedances and...) ... so how would your proposed format handle this?
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