Vince -- I'm all in favor of having this sort of reference design -- but one thoing that worries me is the fact that different boards have different stacks (number of layers, order of layers [esp. power and ground planes], different trace widths and pad sizes and impedances and...) ... so how would your proposed format handle this?
Some of these varying factors can be accommodated in the format by establishing a common set of elements and properties with the assistance of EDA tool vendors, and the leverage of current standards such as IPC-2581. The initiative could be further supported with a style-guide that outlines common stack-ups, conventions, etc. We're really talking about board-level IP reuse across vendor tools. I see silicon IP design reuse as very successful and it has been characterized by style-guides (Reuse Methodology Manual [RMM]), standard design definition formats (Register Transfer Logic [RTL]), syntax checkers, etc. The community could leverage some of these concepts for a workable board-level exchange standard. And just to clarify, I'm not advocating a data standard that can be used to move ALL design data and subtleties from one vendor tool to another; I'm advocating this approach as a means to import reference designs.
@Vince: ...And just to clarify, I'm not advocating a data standard that can be used to move ALL design data and subtleties from one vendor tool to another; I'm advocating this approach as a means to import reference designs.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.