Breaking News
Comments
Newest First | Oldest First | Threaded View
ali haghnegahdar
User Rank
Rookie
3D Manufacturing Semi
ali haghnegahdar   9/10/2013 9:38:48 PM
NO RATINGS
1 saves
3 specialist companies  in 3D chips :

tezzaron semiconductor :

http://www.tezzaron.com/index.html

ziptronix :

http://www.ziptronix.com/

alliva :

http://www.allvia.com/

(activities in 3D research from 2000)

 

ali haghnegahdar
User Rank
Rookie
MPLS networks
ali haghnegahdar   9/10/2013 8:50:55 PM
NO RATINGS
1 saves
Dear Rick : I think if memory vendors can design and produce TCAM(Ternary Content Addressable Memory) memory, RLDRAM 2&3 and QDR-SRAM 2+ in 3d (stacking) big changing in high-end routers and switches, MPLS networks will be faster, improving performance and speed. if T-RAM or Z-RAM will be producing in 3d(stacking) , revolutionize technology in telecom and computer world. T-RAM is a successor for SRAM from T-RAM semiconductor (also successor of DRAM) . http://en.wikipedia.org/wiki/T-RAM http://www.t-ram.com/ Z-RAM (Zero- capacitor RAM) : Z-RAM is a successor for SRAM and DRAM from AMD and SK Hynix. http://en.wikipedia.org/wiki/Z-RAM www.youtube.com/watch?v=PW_7C9kiY6

docdivakar
User Rank
Manager
Re: Where's the Beef ??
docdivakar   8/29/2013 8:48:26 PM
NO RATINGS
Rick, thanks for posting the image! Are there more images made available by Micron or other alliance partners?

I fully concur with Micron team's obsevation on lack of design tools -though things have improved today, there is still a lot to be done.

It would be good to some follow up story on what Gen2 or later HMCs would feature?

MP Divakar

rick merritt
User Rank
Author
Re: Where's the Beef ??
rick merritt   8/23/2013 1:55:35 PM
NO RATINGS
1 saves
Here's an HMC picture from Micron in a response to a request by Chipmonk:



scottstevens12
User Rank
Rookie
Re: Where's the Beef ??
scottstevens12   8/20/2013 9:06:38 PM
NO RATINGS
Thanks for your interest in Micron's Hybrid Memory Cube. As reported, Micron has begun delivering 2GB engineering samples to key customers with HMC system designs. General availability of samples will begin this fall. I've tried to post a SEM photo -- side view of the HMC device just prior to final assembly. If it doesn't show in the window below, just let me know an address where I can email and will be happy to do so.

Picture1Fix.jpg
And to follow the progress of HMC, please feel free to log into micron.com<http://micron.com> and register for additional information about this cool new technology. Or come by and visit us.

rick merritt
User Rank
Author
Re: Where's the Beef ??
rick merritt   8/15/2013 2:45:00 AM
NO RATINGS
@Chipmonk: Thanks for the thoughtful questions.

Anyone from Micron out there that can weigh in on them?

chipmonk0
User Rank
CEO
Where's the Beef ??
chipmonk0   8/14/2013 12:10:58 PM
NO RATINGS
Still showing 3-d chip stacks and packages generated by PPT ! And instead of any technical specifics yet more vague war stories from Sr. Managers !! Weren't they supposed to start shipping their Cube by June this year ?

Meanwhile Samsung has already announced NAND product based on 3-d stack of transistors on a single wafer, not just 3-d stack of chips.

Suggest you go back and ask them for some tangible proof of existence for their Cube ( graphics with a software generated speed meter showing Bandwidth, as displayed at the last 2 IDFs, does'nt cut it any more ), instead need to see SEMs of real stacks & packages, photo of test set up showing the exposed DUT, actual Eye Diagrams from scope shots ... 

The best would be if they gave you access to people actually responsible for putting the thing together. Their Scott Graham gave a talk at SemiCon last month, but ....

Questions one could ask Graham.

How many fully functional units built so far ? What are the issues related to using Copper filled TSVs. How big is the Keep Out Zone around their TSVs to reduce effect on device & consequent loss of die real estate ? Are they looking at alternative fill materials ? What are the issues in first thinning wafers one by one, peeling the thinned wafers from back - up, then stacking & bonding the thinned wafers ( as they seem to be doing ) instead of sequential bonding of thick wafers to a base and then thinning ( Tezzaron ), how do they maintain temperature ( affects refresh rate ) uniformity within a stack ?

All of these issues & quite a few more affect the viability of 3D Memory chips using TSVs.

rick merritt
User Rank
Author
Tell your story
rick merritt   8/14/2013 11:19:08 AM
NO RATINGS
Do you have a story of your part in helping to build the Cube or what you will do with it?


Or a tale of some other 3-D IC?



Flash Poll
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Rishabh N. Mahajani, High School Senior and Future Engineer

Future Engineers: Don’t 'Trip Up' on Your College Road Trip
Rishabh N. Mahajani, High School Senior and Future Engineer
3 comments
A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
19 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
39 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
144 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)