Dear Rick :
I think if memory vendors can design and produce TCAM(Ternary Content Addressable Memory) memory, RLDRAM 2&3 and QDR-SRAM 2+ in 3d (stacking) big changing in high-end routers and switches, MPLS networks will be faster, improving performance and speed.
if T-RAM or Z-RAM will be producing in 3d(stacking) , revolutionize technology in telecom and computer world.
T-RAM is a successor for SRAM from T-RAM semiconductor (also successor of DRAM) .
Z-RAM (Zero- capacitor RAM) :
Z-RAM is a successor for SRAM and DRAM from AMD and SK Hynix.
Thanks for your interest in Micron's Hybrid Memory Cube. As reported, Micron has begun delivering 2GB engineering samples to key customers with HMC system designs. General availability of samples will begin this fall. I've tried to post a SEM photo -- side view of the HMC device just prior to final assembly. If it doesn't show in the window below, just let me know an address where I can email and will be happy to do so.
And to follow the progress of HMC, please feel free to log into micron.com<http://micron.com> and register for additional information about this cool new technology. Or come by and visit us.
Still showing 3-d chip stacks and packages generated by PPT ! And instead of any technical specifics yet more vague war stories from Sr. Managers !! Weren't they supposed to start shipping their Cube by June this year ?
Meanwhile Samsung has already announced NAND product based on 3-d stack of transistors on a single wafer, not just 3-d stack of chips.
Suggest you go back and ask them for some tangible proof of existence for their Cube ( graphics with a software generated speed meter showing Bandwidth, as displayed at the last 2 IDFs, does'nt cut it any more ), instead need to see SEMs of real stacks & packages, photo of test set up showing the exposed DUT, actual Eye Diagrams from scope shots ...
The best would be if they gave you access to people actually responsible for putting the thing together. Their Scott Graham gave a talk at SemiCon last month, but ....
Questions one could ask Graham.
How many fully functional units built so far ? What are the issues related to using Copper filled TSVs. How big is the Keep Out Zone around their TSVs to reduce effect on device & consequent loss of die real estate ? Are they looking at alternative fill materials ? What are the issues in first thinning wafers one by one, peeling the thinned wafers from back - up, then stacking & bonding the thinned wafers ( as they seem to be doing ) instead of sequential bonding of thick wafers to a base and then thinning ( Tezzaron ), how do they maintain temperature ( affects refresh rate ) uniformity within a stack ?
All of these issues & quite a few more affect the viability of 3D Memory chips using TSVs.