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Peter Clarke
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Re: Whoever gets there first...
Peter Clarke   8/27/2013 6:26:01 AM
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But the first penguin of the iceberg can get eaten by the killer whale.

In other words Intel could spend a great deal of money to try and get to production on 450-mm diameter wafers first and then find itself unable to achieve yield or lacking in support from equipment vendors.

It might be that the second and third penguins off the iceberg (called Samsung and TSMC) do better?

Peter Clarke
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Re: D1x -
Peter Clarke   8/27/2013 6:16:28 AM
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Hillsboro, Oregon 

Peter Clarke
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Re: Incredible!
Peter Clarke   8/27/2013 6:15:14 AM
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Engineering is all about the solution of problems.

For example, the weight of a 450-mm wafer is such that it may have to be made thicker just to prevent bowing, which would make the wafer into a concave dish, which would take circuits out of focus.

Do you take the extra mass....but then stage for accelerating and decelerating wafers comes under stress because of extra mass....or do you cope with the bowed wafer ...or can you support wafer...and how do you make machines produce good die across the whole of such a large wafer, or do you tolerate a ring of out of spec die at the edge??

Or does there come a point when the cost of all the extra steps to maintain processing and yield make the transition from 300-mm unworthwhile?

 

 

KB3001
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Whoever gets there first...
KB3001   8/19/2013 7:26:49 AM
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will gain great economies of scale advantages until the others catch up. Intel as ever are banking on technology advances be it at the transistor level or wafer level to gain competitve advantage. If they couple this with architectural changes (ditch x86 in mobile in particular), they would leave the rest of the competition in the dust!

HS_SemiPro
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Re: D1x -
HS_SemiPro   8/19/2013 12:44:46 AM
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D1X should be in Hillsboro, OR.

 

 

J. D.
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D1x -
J. D.   8/16/2013 9:42:17 PM
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in the article - i see TSMC location(s)

D1x location must be embedded (?).

(somewhere)

i guess goggle for D1x location...

Polyspace
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Incredible!
Polyspace   8/16/2013 4:18:28 PM
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I've worked with wafers from 2" though 8", and have been around in a 12" wafer fab. The engineering required for these large wafer sizes is non-trivial. 18" wafer manufacturing is surely pushing the limits? Or, are there limits? Intel keeps pushing the boundaries, they are definitely the leader of the pack!

rick merritt
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Nice catch
rick merritt   8/15/2013 12:39:51 PM
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Nice catch on this semi industry milestone, Peter!



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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