At the Design and Verification Conference last February, there was a panel ("Where Does Design End and Verification Begin?") that discussed the impact of new verification tools that focus on just one problem area and thereby enable more effective verifcation. Engineers no longer have to create a solution out of their own dynamic simulator, static analyzer, or ABV tools.
In the example of Meridian clock-domain-crossing (CDC) verification, a mix of structural, formal and dynamic methods operating under-the-hood, ensure that an SoC will not fail with a metastability issue. Other examples are state-of-the art Lint analysis, and X-propagation and reset verfication / optimization.
At Real Intent, we call this new category Static Verfication. Gary Smith calls them Verification Apps. I see these as important addition to our tool chest so engineers don't design SoCs that we cannot verify.
Blog Doing Math in FPGAs Tom Burke 18 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...